Remove i2c3 and add i2c4 (nxp-imx#7)

Author: vlaarco

arch/arm64/boot/dts/freescale/mt-connect.dts

@@ -321,13 +321,13 @@
 	};
 };
 
-&i2c3 {
+&i2c4 {
 	clock-frequency = <100000>;
 	pinctrl-names = "default", "gpio";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	pinctrl-1 = <&pinctrl_i2c3_gpio>;
-	scl-gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
-	sda-gpios = <&gpio5 19 GPIO_ACTIVE_HIGH>;
+	pinctrl-0 = <&pinctrl_i2c4>;
+	pinctrl-1 = <&pinctrl_i2c4_gpio>;
+	scl-gpios = <&gpio5 20 GPIO_ACTIVE_HIGH>;
+	sda-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
 	status = "okay";
 };
 
@@ -406,29 +406,29 @@
 		fsl,pins =
 		<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
 		<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
-		<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
-		<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
-		<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
-		<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
-		<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
+		<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91>,
+		<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91>,
+		<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91>,
+		<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91>,
+		<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91>,
 		<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
-		<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f>,
-		<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f>,
-		<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f>,
-		<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f>,
-		<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f>,
+		<MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0	0x1f>,
+		<MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1	0x1f>,
+		<MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2	0x1f>,
+		<MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3	0x1f>,
+		<MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC	0x1f>,
 		<MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f>;
 	};
 
 	pinctrl_fec1_sleep: fec1-sleepgrp {
 		fsl,pins =
 		<MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x3>,
 		<MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3>,
-		<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91>,
-		<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91>,
-		<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91>,
-		<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91>,
-		<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91>,
+		<MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0	0x91>,
+		<MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1	0x91>,
+		<MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2	0x91>,
+		<MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3	0x91>,
+		<MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC	0x91>,
 		<MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91>,
 		<MX8MM_IOMUXC_ENET_TD0_GPIO1_IO21		0x1f>,
 		<MX8MM_IOMUXC_ENET_TD1_GPIO1_IO20		0x1f>,
@@ -440,56 +440,56 @@
 
 	pinctrl_ethphy: dhcom-ethphy-grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3			0x1c4
-		MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4			0x1c4
+		MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3		0x1c4
+		MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4		0x1c4
 		>;
 	};
 
 	pinctrl_ir: irgrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13              0x4f
+		MX8MM_IOMUXC_GPIO1_IO13_GPIO1_IO13		0x4f
 		>;
 	};
 
 	pinctrl_i2c1: i2c1grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
-		MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
+		MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
+		MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
 		>;
 	};
 
 	pinctrl_i2c2: i2c2grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
-		MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
+		MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
+		MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
 		>;
 	};
 
-	pinctrl_i2c3: i2c3grp {
+	pinctrl_i2c4: i2c4grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
-		MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
+		MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL		0x400001c3
+		MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA		0x400001c3
 		>;
 	};
 
 	pinctrl_i2c1_gpio: i2c1-gpiogrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14        		0x1c3
-		MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15        	0x1c3
+		MX8MM_IOMUXC_I2C1_SCL_GPIO5_IO14		0x1c3
+		MX8MM_IOMUXC_I2C1_SDA_GPIO5_IO15		0x1c3
 		>;
 	};
 
 	pinctrl_i2c2_gpio: i2c2-gpiogrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16        		0x1c3
-		MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17        	0x1c3
+		MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16		0x1c3
+		MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17		0x1c3
 		>;
 	};
 
-	pinctrl_i2c3_gpio: i2c3-gpiogrp {
+	pinctrl_i2c4_gpio: i2c4-gpiogrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18        		0x1c3
-		MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19        	0x1c3
+		MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20		0x1c3
+		MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21		0x1c3
 		>;
 	};
 
@@ -513,84 +513,84 @@
 
 	pinctrl_sai3: sai3grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC     0xd6
-		MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK      0xd6
-		MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK        0xd6
-		MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0     0xd6
+		MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC		0xd6
+		MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK		0xd6
+		MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK		0xd6
+		MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0		0xd6
 		>;
 	};
 
 	pinctrl_typec1: typec1grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11	0x159
+		MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11		0x159
 		>;
 	};
 
 	pinctrl_uart2: uart2grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
-		MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
+		MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140
+		MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140
 		>;
 	};
 
 	pinctrl_usdhc3: usdhc3grp {
 		fsl,pins = <
-		MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x190
-		MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d0
-		MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d0
-		MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d0
-		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
-		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d0
-		MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d0
-		MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d0
-		MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d0
-		MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d0
-		MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d0
-		MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x190
+		MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
+		MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
+		MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
+		MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
+		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
+		MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
+		MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
+		MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
+		MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
+		MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
+		MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x190
 		>;
 	};
 
 	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x194
-		MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d4
-		MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d4
-		MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d4
-		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d4
-		MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d4
-		MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d4
-		MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d4
-		MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d4
-		MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d4
-		MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x194
+		MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
+		MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
+		MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
+		MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
+		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
+		MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
+		MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
+		MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
+		MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
+		MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
+		MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x194
 		>;
 	};
 
 	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK               0x196
-		MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD               0x1d6
-		MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0           0x1d6
-		MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1           0x1d6
-		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2           0x1d6
-		MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3           0x1d6
-		MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4             0x1d6
-		MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5            0x1d6
-		MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6            0x1d6
-		MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7              0x1d6
-		MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE           0x196
+		MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
+		MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
+		MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
+		MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
+		MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
+		MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
+		MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
+		MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
+		MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
+		MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
+		MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE		0x196
 		>;
 	};
 
 	pinctrl_wdog: wdoggrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
+		MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B		0x166
 		>;
 	};
 
 	pinctrl_backlight: backlightgrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT	0x06
+		MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT		0x06
 		>;
 	};
 
@@ -620,12 +620,12 @@
 &iomuxc {
 	pinctrl_flexspi: flexspigrp {
 		fsl,pins = <
-		MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK               0x1c2
-		MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B            0x82
-		MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0           0x82
-		MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1           0x82
-		MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2           0x82
-		MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3           0x82
+		MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK		0x1c2
+		MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B		0x82
+		MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0		0x82
+		MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1		0x82
+		MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2		0x82
+		MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3		0x82
 		>;
 	};
 };