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MUA91MUA91
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Add basic sound cards and enabled M4 memory (nxp-imx#20)
* Initial sound card integration * Added reserved memory space for Cortex-M4 * Added corrections to SAI clock pads and removed unnecessary IO settings * Override the ALSA slot width. reset it to 32-bit * Fixed wrong bus clock setting * Corrected the clock sync setting of SAI 1,3 so that the RX follows the bit clock of the TX
1 parent 219d017 commit ef6f23e

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+117
-23
lines changed

2 files changed

+117
-23
lines changed

‎arch/arm64/boot/dts/freescale/mt-connect.dts‎

Lines changed: 109 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,25 @@
2525
reg = <0x0 0x40000000 0 0x80000000>;
2626
};
2727

28+
reserved-memory {
29+
#address-cells = <2>;
30+
#size-cells = <2>;
31+
ranges;
32+
33+
/* Coretx-M4 will use TCM section (Tightly Coupled Memory) being much faster than DRAM */
34+
/* 128 kB for Text */
35+
cortex_m4_text: m4@7E0000 {
36+
reg = <0 0x7E0000 0 0x20000>;
37+
no-map;
38+
};
39+
40+
/* 128 kB for Data */
41+
cortex_m4_data: m4@800000 {
42+
reg = <0 0x800000 0 0x20000>;
43+
no-map;
44+
};
45+
};
46+
2847
reg_ldo_vcc: regulator-ldo-vcc {
2948
compatible = "regulator-fixed";
3049
regulator-name = "ldo_vcc_3v3";
@@ -95,6 +114,55 @@
95114
pwms = <&pwm1 0 50000 0>;
96115
};
97116
};
117+
118+
dante_osc_mclk: dante-osc-mclk {
119+
compatible = "fixed-clock";
120+
#clock-cells = <0>;
121+
clock-frequency = <12288000>;
122+
clock-output-names = "dante_osc_mclk";
123+
};
124+
125+
dante_osc_lrclk: dante-osc-lrclk {
126+
compatible = "fixed-clock";
127+
#clock-cells = <0>;
128+
clock-frequency = <48000>;
129+
clock-output-names = "dante_osc_lrclk";
130+
};
131+
132+
dante_osc_sclk: dante-osc-sclk {
133+
compatible = "fixed-clock";
134+
#clock-cells = <0>;
135+
clock-frequency = <12288000>;
136+
clock-output-names = "dante_osc_sclk";
137+
};
138+
139+
sound_interprocessor {
140+
compatible = "fsl,imx-audio-card";
141+
model = "imx-audio-card";
142+
pri-dai-link {
143+
link-name = "interproc audio";
144+
format = "i2s";
145+
fsl,mclk-equal-bclk;
146+
cpu {
147+
sound-dai = <&sai1>;
148+
dai-tdm-slot-width = <32>;
149+
};
150+
};
151+
};
152+
153+
sound_Headphone {
154+
compatible = "fsl,imx-audio-card";
155+
model = "imx-audio-card"; /*Dummy Codec*/
156+
pri-dai-link {
157+
link-name = "Headphone audio";
158+
format = "i2s";
159+
fsl,mclk-equal-bclk;
160+
cpu {
161+
sound-dai = <&sai3>;
162+
dai-tdm-slot-width = <32>;
163+
};
164+
};
165+
};
98166
};
99167

100168
&A53_0 {
@@ -327,6 +395,29 @@
327395
status = "okay";
328396
};
329397

398+
&sai3 {
399+
pinctrl-names = "default";
400+
pinctrl-0 = <&pinctrl_sai3>;
401+
clocks = <&clk IMX8MM_CLK_SAI3_IPG>, <&clk IMX8MM_CLK_DUMMY>,
402+
<&dante_osc_sclk>,
403+
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
404+
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
405+
fsl,txs-rxs;
406+
status = "okay";
407+
};
408+
409+
&sai1 {
410+
pinctrl-names = "default";
411+
pinctrl-0 = <&pinctrl_sai1>;
412+
clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
413+
<&dante_osc_sclk>,
414+
<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
415+
clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
416+
fsl,dataline = <1 0x0F 0x0F>; /*I2S mode enabled, 4 TX lines, 4 RX lines*/
417+
fsl,txs-rxs;
418+
status = "okay";
419+
};
420+
330421
&snvs_pwrkey {
331422
status = "okay";
332423
};
@@ -511,49 +602,46 @@
511602
>;
512603
};
513604

514-
pinctrl_pdm: pdmgrp {
605+
pinctrl_pmic: pmicirqgrp {
515606
fsl,pins = <
516-
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
517-
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
518-
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
519-
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
520-
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
521-
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
522-
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
607+
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
523608
>;
524609
};
525610

526-
pinctrl_pdm: pdmgrp {
611+
pinctrl_sai1: sai1grp {
527612
fsl,pins = <
528-
MX8MM_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6
529-
MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6
530-
MX8MM_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6
531-
MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6
532-
MX8MM_IOMUXC_SAI5_RXD1_PDM_DATA1 0xd6
533-
MX8MM_IOMUXC_SAI5_RXD2_PDM_DATA2 0xd6
534-
MX8MM_IOMUXC_SAI5_RXD3_PDM_DATA3 0xd6
613+
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0x80
614+
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0x80
615+
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
616+
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
617+
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
618+
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
619+
MX8MM_IOMUXC_SAI1_RXD0_SAI1_RX_DATA0 0xd6
620+
MX8MM_IOMUXC_SAI1_RXD1_SAI1_RX_DATA1 0xd6
621+
MX8MM_IOMUXC_SAI1_RXD2_SAI1_RX_DATA2 0xd6
622+
MX8MM_IOMUXC_SAI1_RXD3_SAI1_RX_DATA3 0xd6
535623
>;
536624
};
537625

538-
pinctrl_pmic: pmicirqgrp {
626+
627+
pinctrl_sai3: sai3grp {
539628
fsl,pins = <
540-
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x141
629+
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0x80 /* DANTE_OSC_SCLK */
630+
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6 /* DPM_HP_DAC_SD */
631+
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0x80 /* DPM_HP_DAC_LRCK */
541632
>;
542633
};
543634

544635
pinctrl_gpio4: gpio4grp {
545636
fsl,pins = <
546637
MX8MM_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x06 /* HP_DAC_PDN */
547638
MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x06 /* HP_DAC_I2C_FIL */
548-
MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x80 /* DPM_HP_DAC_LRCK */
549639
>;
550640
};
551641

552642
pinctrl_gpio5: gpio5grp {
553643
fsl,pins = <
554-
MX8MM_IOMUXC_SAI3_TXC_GPIO5_IO0 0x80 /* DANTE_OSC_BICK */
555644
MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x80 /* DANTE_OSC_MCLK */
556-
MX8MM_IOMUXC_SAI3_TXD_GPIO5_IO1 0x06 /* DPM_HP_DAC_SD */
557645
>;
558646
};
559647

‎sound/soc/fsl/fsl_sai.c‎

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -168,10 +168,11 @@ static irqreturn_t fsl_sai_isr(int irq, void *devid)
168168
static int fsl_sai_set_dai_tdm_slot(struct snd_soc_dai *cpu_dai, u32 tx_mask,
169169
u32 rx_mask, int slots, int slot_width)
170170
{
171+
(void)(slot_width); /*Override the ALSA slot width setting*/
171172
struct fsl_sai *sai = snd_soc_dai_get_drvdata(cpu_dai);
172173

173174
sai->slots = slots;
174-
sai->slot_width = slot_width;
175+
sai->slot_width = 32u;
175176

176177
return 0;
177178
}
@@ -610,7 +611,7 @@ static int fsl_sai_hw_params(struct snd_pcm_substream *substream,
610611
if (sai->is_lsb_first || sai->is_pdm_mode)
611612
val_cr5 |= FSL_SAI_CR5_FBT(0);
612613
else
613-
val_cr5 |= FSL_SAI_CR5_FBT(word_width - 1);
614+
val_cr5 |= FSL_SAI_CR5_FBT(slot_width - 1);
614615

615616
val_cr4 |= FSL_SAI_CR4_FRSZ(slots);
616617

@@ -1436,6 +1437,11 @@ static int fsl_sai_probe(struct platform_device *pdev)
14361437
if (of_find_property(np, "fsl,txm-rxs", NULL) != NULL) {
14371438
sai->masterflag[FSL_FMT_TRANSMITTER] = SND_SOC_DAIFMT_BP_FP;
14381439
sai->masterflag[FSL_FMT_RECEIVER] = SND_SOC_DAIFMT_BC_FC;
1440+
} else if (of_find_property(np, "fsl,txs-rxs", NULL) != NULL) {
1441+
sai->masterflag[FSL_FMT_TRANSMITTER] = SND_SOC_DAIFMT_BC_FC;
1442+
sai->masterflag[FSL_FMT_RECEIVER] = SND_SOC_DAIFMT_BC_FC;
1443+
} else {
1444+
/*Do nothing*/
14391445
}
14401446

14411447
irq = platform_get_irq(pdev, 0);

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