Merge pull request #159 from PurdueElectricRacing/feature/cmcgalliard/rcc-MCO

[READY] Clock Out MCO1

Author: mcgalliard

common/phal_F4_F7/gpio/gpio.h

@@ -232,6 +232,9 @@ typedef struct
 #define GPIO_INIT_SDIO_DT2  GPIO_INIT_AF(GPIOC, 10, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
 #define GPIO_INIT_SDIO_DT3  GPIO_INIT_AF(GPIOC, 11, 12, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_PULL_UP)
 
+// MCO1 (AF0)
+#define GPIO_INIT_MCO1_PA8 GPIO_INIT_AF(GPIOA, 8, 0, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
+
 #ifdef STM32F732xx
 //CAN
 #define GPIO_INIT_CANRX_PA11 GPIO_INIT_AF(GPIOA, 11, 9, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_OPEN_DRAIN, GPIO_INPUT_OPEN_DRAIN)
@@ -240,6 +243,8 @@ typedef struct
 
 //SPI
 
+// MCO1 (AF0)
+#define GPIO_INIT_MCO1_PA8 GPIO_INIT_AF(GPIOA, 8, 0, GPIO_OUTPUT_ULTRA_SPEED, GPIO_OUTPUT_PUSH_PULL, GPIO_INPUT_OPEN_DRAIN)
 
 
 //UART/USART

common/phal_F4_F7/rcc/rcc.c

@@ -382,3 +382,28 @@ void PHAL_trimHSI(uint8_t trim_val)
     reg |= trim_val << RCC_CR_HSITRIM_Pos;
     RCC->CR = reg;
 }
+
+bool PHAL_enableMCO1(GPIO_TypeDef* bank, uint8_t pin, MCO1Source_t source, MCODivisor_t division)
+{
+    if ((bank == GPIOA) && (pin == MCO_OUT_PIN))
+    {
+        /* Clear Previous MCO1 Source */
+        RCC->CFGR &= ~(RCC_CFGR_MCO1_Msk);
+
+        /* Select MCO1 Source*/
+        RCC->CFGR |= (source << RCC_CFGR_MCO1_Pos);
+
+        /* Clear Previous Prescaler */
+        RCC->CFGR &= ~(RCC_CFGR_MCO1PRE_Msk);
+
+        /* Select MCO1 Prescaler */
+        RCC->CFGR |= (division << RCC_CFGR_MCO1PRE_Pos);
+    }
+    else
+    {
+        return false;
+    }
+
+    return true;
+
+} /* PHAL_enableMCO1() */

common/phal_F4_F7/rcc/rcc.h

@@ -30,6 +30,7 @@
 #endif  // HSE_CLOCK_RATE_HZ
 
 #define HSI_CLOCK_RATE_HZ (16000000)
+#define MCO_OUT_PIN (8)
 
 
 // RCC Constants
@@ -61,6 +62,24 @@ typedef enum {
     PLL_SRC_HSI16,
 } PLLSrc_t;
 
+typedef enum
+{
+    MCO1_SRC_HSI = 0,
+    MCO1_SRC_LSE = 1,
+    MCO1_SRC_HSE = 2,
+    MCO1_SRC_PLL = 3,
+
+} MCO1Source_t;
+
+typedef enum
+{
+    MCO_DIV_NONE = 0,
+    MCO_DIV_2    = 4,
+    MCO_DIV_3    = 5,
+    MCO_DIV_4    = 6,
+    MCO_DIV_5    = 7
+
+} MCODivisor_t;
 
 typedef enum {
     SYSTEM_CLOCK_SRC_PLL,
@@ -157,4 +176,23 @@ bool PHAL_configureAPB2Clock(uint32_t apb2_clock_target_hz);
  */
 void PHAL_trimHSI(uint8_t trim_val);
 
+/**
+ * @brief Enable the Clock Out Pin 1
+ *  It is highly recommended to change this
+ *  only after reset before enabling the
+ *  external oscillators and the PLL.
+ * 
+ *  This function should be called after GPIO initialization using 
+ *   GPIO_INIT_MCO1_PA8
+ *
+ * @param bank GPIO bank
+ * @param pin GPIO bank
+ * @param source Clock source to send to the pin
+ * @param division Division of clock source sent to the pin
+ * @return true Successfully enabled the clock out
+ * @return false
+ */
+
+bool PHAL_enableMCO1(GPIO_TypeDef* bank, uint8_t pin, MCO1Source_t source, MCODivisor_t division);
+
 #endif // _PHAL_PLL_H_