CSP ignores 3-or-more-qubit gates

[1ucian0]

Information

• Qiskit Terra version: main

What is the current behavior?

Take the following circuit:

from qiskit import QuantumCircuit
qc = QuantumCircuit(3)
qc.cx(0,1)
qc.ccx(2,0,1)
qc.draw()

q_0: ──■────■──
     ┌─┴─┐┌─┴─┐
q_1: ┤ X ├┤ X ├
     └───┘└─┬─┘
q_2: ───────■──

CSPLayout should not be able to find a solution with a layout 0- > 1 -> 2. However:

from qiskit.transpiler import CouplingMap
from qiskit.transpiler.passes import CSPLayout

pass_ = CSPLayout(CouplingMap([(0, 1), (1, 2)]))
result = pass_(qc)
pass_.property_set["CSPLayout_stop_reason"]

'solution found'

Suggested solutions

There are two options. If CSPLayout encounters a 3-or-more-qubit gate, either assumes that this needs complete connection among the involved qubits, or just fails with reason 3-or-more-qubit gate found.

[yjt98765]

@1ucian0 I tried to add 3-or-more-qubit gates as constraints, and the pass generates this layout:

Layout({
1: Qubit(QuantumRegister(3, 'qr'), 0),
0: Qubit(QuantumRegister(3, 'qr'), 1),
2: Qubit(QuantumRegister(3, 'qr'), 2)
})

I guess maybe it is reasonable? It does not involve swaps. It simply suggests that mapping qr[0] to physical qubit 1. Such mapping is allowed, right? It is kind of the point of using CSP in this pass.

[1ucian0]

In the original example, CCX does not have a possible layout in the coupling map 0 - > 1 -> 2. No solution should be found or raise.

[Silrem]

Can I work on this?

[1ucian0]

Sure thing @Silrem. Assigning. let me know if I can help!

[Silrem]

@1ucian0 Just created a PR (#7625). Not sure if I can/should add you as a reviewer. Anyway, my first draft is there =)