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[bsp][Infineon]add drv_eth (#9527)
[bsp][Infineon]add xmc7200 eth driver #9527 --------- Co-authored-by: LZerro <[email protected]>
1 parent 5010c17 commit 8c1cd39

31 files changed

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-49
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bsp/Infineon/libraries/HAL_Drivers/SConscript

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@@ -59,6 +59,9 @@ if GetDepend(['RT_USING_DAC']):
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if GetDepend(['BSP_USING_TIM']):
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src += ['drv_hwtimer.c']
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if GetDepend(['BSP_USING_ETH']):
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src += ['drv_eth.c']
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path = [cwd]
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path += [cwd + '/config']
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bsp/Infineon/libraries/HAL_Drivers/drv_adc.c

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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#if defined(BSP_USING_ADC1) || defined(BSP_USING_ADC2)
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//#define DRV_DEBUG
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/*#define DRV_DEBUG*/
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#define LOG_TAG "drv.adc"
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#include <drv_log.h>
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@@ -45,9 +45,9 @@ static rt_err_t ifx_adc_enabled(struct rt_adc_device *device, rt_uint32_t channe
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const cyhal_adc_channel_config_t channel_config =
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{
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.enable_averaging = false, // Disable averaging for channel
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.min_acquisition_ns = 1000, // Minimum acquisition time set to 1us
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.enabled = enabled // Sample this channel when ADC performs a scan
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.enable_averaging = false, /* Disable averaging for channel*/
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.min_acquisition_ns = 1000, /* Minimum acquisition time set to 1us*/
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.enabled = enabled /* Sample this channel when ADC performs a scan*/
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};
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if (enabled)

bsp/Infineon/libraries/HAL_Drivers/drv_adc.h

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
@@ -28,13 +28,13 @@ cyhal_adc_channel_t adc_chan_obj;
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const cyhal_adc_config_t adc_config =
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{
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.continuous_scanning = false, // Continuous Scanning is disabled
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.average_count = 1, // Average count disabled
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.vref = CYHAL_ADC_REF_VDDA, // VREF for Single ended channel set to VDDA
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.vneg = CYHAL_ADC_VNEG_VSSA, // VNEG for Single ended channel set to VSSA
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.resolution = 12u, // 12-bit resolution
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.ext_vref = NC, // No connection
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.bypass_pin = NC // No connection
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.continuous_scanning = false, /* Continuous Scanning is disabled*/
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.average_count = 1, /* Average count disabled*/
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.vref = CYHAL_ADC_REF_VDDA, /* VREF for Single ended channel set to VDDA*/
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.vneg = CYHAL_ADC_VNEG_VSSA, /* VNEG for Single ended channel set to VSSA*/
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.resolution = 12u, /* 12-bit resolution*/
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.ext_vref = NC, /* No connection*/
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.bypass_pin = NC /* No connection*/
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};
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#ifndef ADC1_CONFIG

bsp/Infineon/libraries/HAL_Drivers/drv_common.c

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*

bsp/Infineon/libraries/HAL_Drivers/drv_common.h

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*

bsp/Infineon/libraries/HAL_Drivers/drv_dac.c

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*

bsp/Infineon/libraries/HAL_Drivers/drv_dac.h

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*

bsp/Infineon/libraries/HAL_Drivers/drv_eth.c

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/*
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2024-09-23 LZerro first version
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*/
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#ifndef __DRV_ETH_H__
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#define __DRV_ETH_H__
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#include <rtthread.h>
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#include <rthw.h>
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#include <rtdevice.h>
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#include <board.h>
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#include "eth_config.h"
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/* The PHY basic control register */
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#define PHY_BASIC_CONTROL_REG 0x00U
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#define PHY_RESET_MASK (1<<15)
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#define PHY_AUTO_NEGOTIATION_MASK (1<<12)
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/* The PHY basic status register */
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#define PHY_BASIC_STATUS_REG 0x01U
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#define PHY_LINKED_STATUS_MASK (1<<2)
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#define PHY_AUTONEGO_COMPLETE_MASK (1<<5)
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/* The PHY ID one register */
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#define PHY_ID1_REG 0x02U
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/* The PHY ID two register */
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#define PHY_ID2_REG 0x03U
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/* The PHY auto-negotiate advertise register */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U
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/** PHY duplex mode */
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typedef enum
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{
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CY_ECM_DUPLEX_HALF, /**< Half duplex */
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CY_ECM_DUPLEX_FULL, /**< Full duplex */
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CY_ECM_DUPLEX_AUTO /**< Both half/full duplex */
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} cy_ecm_duplex_t;
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/** PHY speed */
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typedef enum
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{
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CY_ECM_PHY_SPEED_10M, /**< 10 Mbps */
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CY_ECM_PHY_SPEED_100M, /**< 100 Mbps */
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CY_ECM_PHY_SPEED_1000M, /**< 1000 Mbps */
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CY_ECM_PHY_SPEED_AUTO /**< All 10/100/1000 Mbps */
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} cy_ecm_phy_speed_t;
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/** Standard interface type */
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typedef enum
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{
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CY_ECM_SPEED_TYPE_MII, /**< Media-Independent Interface (MII) */
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CY_ECM_SPEED_TYPE_GMII, /**< Gigabit Media-Independent Interface (GMII) */
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CY_ECM_SPEED_TYPE_RGMII, /**< Reduced Gigabit Media-Independent Interface (RGMII) */
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CY_ECM_SPEED_TYPE_RMII /**< Reduced Media-Independent Interface (RMII) */
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} cy_ecm_speed_type_t;
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typedef struct
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{
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cy_ecm_speed_type_t interface_speed_type; /**< Standard interface to be used for data transfer */
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cy_ecm_phy_speed_t phy_speed; /**< Physical transfer speed */
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cy_ecm_duplex_t mode; /**< Transfer mode */
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} cy_ecm_phy_config_t;
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extern int eth_index_internal;
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#define ETH_INTERFACE_TYPE ETH1
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/* After hardware initialization, max wait time to get the physical link up */
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#define MAX_WAIT_ETHERNET_PHY_STATUS (10000)
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#define REGISTER_ADDRESS_PHY_REG_BMCR PHYREG_00_BMCR /* BMCR register (0x0000) to read the speed and duplex mode */
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#define REGISTER_PHY_REG_DUPLEX_MASK PHYBMCR_FULL_DUPLEX_Msk /* Bit 8 of BMCR register to read the duplex mode */
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#define REGISTER_PHY_REG_SPEED_MASK (0x2040) /* Bit 6, 13: BMCR register to read the speed */
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#define REGISTER_PHY_REG_SPEED_MASK_10M (0x0000) /* Bit 6, 13: Both are set to 0 for 10M speed */
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#define REGISTER_PHY_REG_SPEED_MASK_100M (0x2000) /* Bit 6, 13: Set to 0 and 1 respectively for 100M speed */
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#define REGISTER_PHY_REG_SPEED_MASK_1000M (0x0040) /* Bit 6, 13: Set to 1 and 0 respectively for 1000M speed */
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#endif /* __DRV_ETH_H__ */
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bsp/Infineon/libraries/HAL_Drivers/drv_flash.c

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/*
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* Copyright (c) 2006-2023, RT-Thread Development Team
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* Copyright (c) 2006-2024 RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*

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