[Arch/RISC-V] Next RISC-V

1. ISA manager interface.
2. Merge 32E/32I/64I.
3. Cache by CBOM ISA.
4. MMU support Sv32/Sv39/Sv48/Sv57/Sv64, SVPBMT ISA.
5. Merge M-mode, S-mode CSR ops.
6. Support SMP.
7. Support APLIC & IMSIC (AIA), CLIC, ACLINT/CLINT, INTC, PLIC.
8. Support DM (only by OFW) or not DM.
9. Merge T-HEAD vendor.

Signed-off-by: GuEe-GUI <[email protected]>

Author: GuEe-GUI

libcpu/Kconfig

@@ -2,6 +2,10 @@ if ARCH_ARMV8 && ARCH_CPU_64BIT
     orsource "./aarch64/Kconfig"
 endif
 
+if ARCH_RISCV
+    orsource "./risc-v/Kconfig"
+endif
+
 config ARCH_CPU_64BIT
     bool
 
@@ -195,7 +199,7 @@ config ARCH_ARMV8
     select ARCH_ARM
     select ARCH_ARM_MMU
     select RT_USING_CPU_FFS
-    select ARCH_USING_ASID
+    select ARCH_USING_ASID if RT_USING_SMART
     select ARCH_USING_IRQ_CTX_LIST
 
 config ARCH_MIPS
@@ -220,55 +224,8 @@ config ARCH_POWERPC
 
 config ARCH_RISCV
     bool
-
-config ARCH_RISCV_FPU
-    bool
-
-config ARCH_RISCV_VECTOR
-    bool
-
-    if ARCH_RISCV_VECTOR
-        choice
-            prompt "RISCV Vector Vlen"
-            default ARCH_VECTOR_VLEN_128
-
-            config ARCH_VECTOR_VLEN_128
-                bool "128"
-            config ARCH_VECTOR_VLEN_256
-                bool "256"
-        endchoice
-    endif
-
-config ARCH_RISCV_FPU_S
-    select ARCH_RISCV_FPU
-    bool
-
-config ARCH_RISCV_FPU_D
-    select ARCH_RISCV_FPU
-    bool
-
-config ARCH_RISCV32
-    select ARCH_RISCV
-    bool
-
-config ARCH_RISCV64
-    select ARCH_RISCV
-    select ARCH_CPU_64BIT
-    bool
-
-if ARCH_RISCV64
-    config ARCH_USING_NEW_CTX_SWITCH
-        bool
-        default y
-
-    config ARCH_USING_RISCV_COMMON64
-        bool
-        depends on ARCH_RISCV64
-        select RT_USING_CPUTIME
-        select ARCH_USING_NEW_CTX_SWITCH
-        help
-            Using the common64 implementation under ./libcpu/risc-v
-endif
+    select RT_USING_CPU_FFS
+    select RT_PAGE_MPR_SIZE_DYNAMIC if ARCH_MM_MMU
 
 config ARCH_REMAP_KERNEL
     bool

libcpu/risc-v/.gitignore

@@ -0,0 +1 @@
+link.lds

libcpu/risc-v/Kconfig

@@ -0,0 +1,91 @@
+menu "RISC-V Architecture Configuration"
+    config ARCH_TEXT_OFFSET
+        hex "Text offset"
+        default 0x200000
+        help
+          We use the area as the DM ioremap address space in 32 bits RT-Thread:
+                [ARCH_TEXT_OFFSET - IOREMAP_SIZE, ARCH_TEXT_OFFSET)
+          So you SHOULD config the value bigger than this area.
+          The `IOREMAP_SIZE` is defined a default value in common/setup.c.
+
+    config ARCH_RAM_OFFSET
+        hex "RAM offset"
+        default 0
+
+    config ARCH_SECONDARY_CPU_STACK_SIZE
+        int "Secondary CPU stack size"
+        default 4096
+
+    config ARCH_HAVE_EFFICIENT_UNALIGNED_ACCESS
+        bool
+        default y
+
+    config ARCH_HEAP_SIZE
+        hex "Size of system heap"
+        default 0x4000000
+
+    config ARCH_INIT_PAGE_SIZE
+        hex "Size of init page region"
+        default 0x200000
+
+    config ARCH_RISCV_DISABLE_FENCE_I
+        bool
+        default n
+
+    config ARCH_RISCV_DISABLE_SFENCE_VMA_ASID
+        bool
+        default n
+
+    config ARCH_RISCV_M_MODE
+        bool
+        depends on !ARCH_MM_MMU
+        default n
+
+    config ARCH_RISCV_32E
+        bool
+        depends on !ARCH_CPU_64BIT
+        depends on !ARCH_MM_MMU
+        depends on !RT_USING_DM
+
+    config ARCH_RISCV_FPU
+        bool "Enable FPU"
+        default y
+
+    config ARCH_RISCV_VECTOR
+        bool "Using RISC-V Vector Extension"
+        depends on !ARCH_RISCV_32E
+
+    choice
+        prompt "Vector Registers Length in Bits"
+        depends on ARCH_RISCV_VECTOR
+        default ARCH_VECTOR_VLEN_128
+
+        config ARCH_VECTOR_VLEN_128
+            bool "128"
+        config ARCH_VECTOR_VLEN_256
+            bool "256"
+    endchoice
+
+    config ARCH_RISCV_FPU_S
+        select ARCH_RISCV_FPU
+        bool
+
+    config ARCH_RISCV_FPU_D
+        select ARCH_RISCV_FPU
+        bool
+
+    config ARCH_USING_NEW_CTX_SWITCH
+        bool
+        depends on ARCH_CPU_64BIT
+        default y
+
+    config ARCH_USING_RISCV_COMMON64
+        bool
+        depends on ARCH_CPU_64BIT
+        select RT_USING_CPUTIME
+        select ARCH_USING_NEW_CTX_SWITCH
+
+    config RT_USING_USERSPACE_32BIT_LIMIT
+        bool "Enable userspace 32bit limit"
+        default n
+endmenu

libcpu/risc-v/SConscript

@@ -5,23 +5,38 @@ from building import *
 
 Import('rtconfig')
 
-common64_arch = ['virt64', 'c906', 'c908']
 cwd   = GetCurrentDir()
 group = []
 list  = os.listdir(cwd)
+bsp_path = Dir('#').abspath
+vender_path = cwd
 
-# add common code files
-if rtconfig.CPU in common64_arch :
-    group += SConscript(os.path.join('common64', 'SConscript'))
-else :
-    group += SConscript(os.path.join('common', 'SConscript'))
+if not os.path.exists(bsp_path + "/link.lds"):
+    Env['LINKFLAGS'] = Env['LINKFLAGS'].replace('link.lds', cwd + "/link.lds")
+    Preprocessing("link.lds.S", ".lds", CPPPATH=[bsp_path, cwd + '/common/include'])
+
+# fix the linker with crtx.o
+Env['LINKFLAGS'] += ' -nostartfiles'
 
-group += SConscript(os.path.join('vector', 'SConscript'))
+# add common code files
+group += SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-if 'VENDOR' in vars(rtconfig) and rtconfig.VENDOR != '':
-    group = group + SConscript(os.path.join(rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
-elif rtconfig.CPU in list:
+if 'VENDER' in vars(rtconfig) and rtconfig.VENDER != '':
+    group = group + SConscript(os.path.join(rtconfig.VENDER, rtconfig.CPU, 'SConscript'))
+    vender_path += rtconfig.VENDER + "/" + rtconfig.CPU
+elif rtconfig.CPU != '':
     group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
+    vender_path += rtconfig.CPU
+
+if os.path.exists(vender_path + "/mmu_vendor.h"):
+    Env['ASFLAGS']  += '-D__HAS_MMU_VENDOR__'
+    Env['CFLAGS']   += '-D__HAS_MMU_VENDOR__'
+    Env['CXXFLAGS'] += '-D__HAS_MMU_VENDOR__'
+
+if os.path.exists(vender_path + "/opcode_vendor.h"):
+    Env['ASFLAGS']  += '-D__HAS_OPCODE_VENDOR__'
+    Env['CFLAGS']   += '-D__HAS_OPCODE_VENDOR__'
+    Env['CXXFLAGS'] += '-D__HAS_OPCODE_VENDOR__'
 
 Return('group')