fpga.yaml: add example 'with:' VERILOG_DEFINES and YOSYS_ARGS#6

dlmiles wants to merge 1 commit intoTinyTapeout:mainTinyTapeout/ttsky-verilog-template:mainfrom

dlmiles:main-fpga-with-examplesdlmiles/ttsky-verilog-template:main-fpga-with-examplesCopy head branch name to clipboard