Skip to content

Commit 8032fa7

Browse files
committed
Add LEF output for ROM
1 parent 05884cf commit 8032fa7

File tree

3 files changed

+15
-3
lines changed

3 files changed

+15
-3
lines changed

compiler/modules/rom_bank.py

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,14 @@
1111
from openram.base import vector
1212
from openram.base import design
1313
from openram.base import rom_verilog
14+
from openram.base import lef
1415
from openram import OPTS, print_time
1516
from openram.sram_factory import factory
1617
from openram.tech import spice
1718
from openram.tech import drc, layer, parameter
1819

1920

20-
class rom_bank(design,rom_verilog):
21+
class rom_bank(design, rom_verilog, lef):
2122

2223
"""
2324
Rom data bank with row and column decoder + control logic
@@ -27,6 +28,7 @@ class rom_bank(design,rom_verilog):
2728

2829
def __init__(self, name, rom_config):
2930
super().__init__(name=name)
31+
lef.__init__(self, ["m1", "m2", "m3", "m4"])
3032
self.rom_config = rom_config
3133
rom_config.set_local_config(self)
3234

compiler/rom.py

Lines changed: 10 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,9 @@ def __init__(self, rom_config=None, name=None):
5959
def sp_write(self, name, lvs=False, trim=False):
6060
self.r.sp_write(name, lvs, trim)
6161

62+
def lef_write(self, name):
63+
self.r.lef_write(name)
64+
6265
def gds_write(self, name):
6366
self.r.gds_write(name)
6467

@@ -106,6 +109,13 @@ def save(self):
106109
output_path=OPTS.output_path)
107110
print_time("GDS", datetime.datetime.now(), start_time)
108111

112+
# Create a LEF physical model
113+
start_time = datetime.datetime.now()
114+
lefname = OPTS.output_path + self.r.name + ".lef"
115+
debug.print_raw("LEF: Writing to {0}".format(lefname))
116+
self.lef_write(lefname)
117+
print_time("LEF", datetime.datetime.now(), start_time)
118+
109119
# Save the LVS file
110120
start_time = datetime.datetime.now()
111121
lvsname = OPTS.output_path + self.r.name + ".lvs.sp"

rom_compiler.py

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -51,7 +51,7 @@
5151
output_extensions = [ "sp", "v"]
5252
# Only output lef/gds if back-end
5353
if not OPTS.netlist_only:
54-
output_extensions.extend(["gds"])
54+
output_extensions.extend(["lef", "gds"])
5555

5656
output_files = ["{0}{1}.{2}".format(OPTS.output_path,
5757
OPTS.output_name, x)
@@ -69,4 +69,4 @@
6969

7070
# Delete temp files etc.
7171
openram.end_openram()
72-
openram.print_time("End", datetime.datetime.now(), start_time)
72+
openram.print_time("End", datetime.datetime.now(), start_time)

0 commit comments

Comments
 (0)