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SDA USRsdausr
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Squashed 'motor_control' changes from 07deeea..8f8b45c (#1190)
8f8b45c Merge pull request #380 from ryanw/mklab0408 3b5444c updated MKLabs for IP_VOLTAGE_MODULATION Co-authored-by: sdausr <[email protected]>
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-29
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5 files changed

+42
-29
lines changed

‎motor_control/L1/include/hw/apc/common_definitions.hpp‎

Lines changed: 2 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -104,15 +104,13 @@ void PI_Control_stream_Inst(hls::stream<ap_int<BIT_WIDTH_DATA> >& s_axis,
104104
ap_int<BIT_WIDTH_DATA> mode);
105105
void voltage_modulation_inst(hls::stream<ap_uint<BIT_WIDTH_STREAM_FOC> >& s_axis,
106106
hls::stream<ap_int<BIT_WIDTH_DATA> >& voltage_in,
107-
hls::stream<ap_uint<PWM_DATA_TYPE_> >& Va_out,
108-
hls::stream<ap_uint<PWM_DATA_TYPE_> >& Vb_out,
109-
hls::stream<ap_uint<PWM_DATA_TYPE_> >& Vc_out,
110-
// hls::stream< ap_uint< 96 > > &output_s,
107+
hls::stream<ap_uint<96> >& output_s,
111108
hls::stream<ap_uint<BIT_WIDTH_LOG_STREAM_FOC> >& logger_stream_in,
112109
hls::stream<ap_uint<BIT_WIDTH_LOG_STREAM_FOC> >& logger_stream_out,
113110
volatile unsigned int& mode,
114111
volatile int& max_sym_interval,
115112
volatile int& double_interval,
113+
volatile int& scaling_interval_pwm,
116114
volatile int& phase_a,
117115
volatile int& phase_b,
118116
volatile int& phase_c);

‎motor_control/L1/include/hw/apc/common_vars.hpp‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -137,7 +137,10 @@ bool CheckRange(T& v, RangeDef<T>& rg) {
137137
#define BIT_WIDTH_STREAM_FOC 128
138138
#define BIT_WIDTH_LOG_STREAM_FOC 512
139139
#define BIT_WIDTH_STEP_STREAM 32
140+
#define BIT_WIDTH_ADC 24
141+
140142
#define PWM_DATA_TYPE_ 16
143+
#define PWM_DATA_TYPE_3_PHASE 96
141144

142145
#define MIN_IA_LOGGER 0
143146
#define MAX_IA_LOGGER 31

‎motor_control/L1/include/hw/apc/voltage_modulation.hpp‎

Lines changed: 20 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -25,17 +25,21 @@
2525

2626
enum VMMode : unsigned int { PS_DC_REF = 0, PL_DC_REF = 1 };
2727

28-
template <typename T_FOC, typename T_STREAM_LOG, typename WIDTH_DATA, typename WIDTH_ACCUM, typename PWM_DATA_TYPE>
28+
template <typename T_FOC,
29+
typename T_STREAM_LOG,
30+
typename WIDTH_DATA,
31+
typename WIDTH_ACCUM,
32+
typename PWM_DATA_TYPE,
33+
typename PWM_3_PHASE>
2934
void voltage_modulation(hls::stream<T_FOC>& s_axis,
3035
hls::stream<WIDTH_DATA>& voltage_in,
31-
hls::stream<PWM_DATA_TYPE>& Va_out,
32-
hls::stream<PWM_DATA_TYPE>& Vb_out,
33-
hls::stream<PWM_DATA_TYPE>& Vc_out,
36+
hls::stream<PWM_3_PHASE>& output_s,
3437
hls::stream<T_STREAM_LOG>& logger_stream_in,
3538
hls::stream<T_STREAM_LOG>& logger_stream_out,
3639
volatile unsigned int& mode,
3740
volatile int& max_sym_interval,
3841
volatile int& double_interval,
42+
volatile int& scaling_interval_pwm,
3943
volatile int& phase_a,
4044
volatile int& phase_b,
4145
volatile int& phase_c) {
@@ -48,13 +52,16 @@ void voltage_modulation(hls::stream<T_FOC>& s_axis,
4852
WIDTH_ACCUM Va_pwm, Vb_pwm, Vc_pwm;
4953
WIDTH_DATA Va, Vb, Vc;
5054
PWM_DATA_TYPE pwm_mod_a, pwm_mod_b, pwm_mod_c;
55+
PWM_3_PHASE pwm_packet;
5156
volatile int voltage_mod_in;
5257
volatile int double_voltage_mod_in;
5358

5459
const WIDTH_DATA VOLTAGE = 1365; // 1 /48 -> 1/24 not taking into account sign
5560
const WIDTH_DATA MIN_LIM = 0;
56-
const WIDTH_DATA MAX_LIM = 65535;
57-
const ap_uint<BIT_WIDTH_FRACTIONAL> HALF = 32768;
61+
// const WIDTH_DATA MAX_LIM = 65535;
62+
// const ap_uint<BIT_WIDTH_FRACTIONAL> HALF = 32768;
63+
const WIDTH_DATA MAX_LIM = scaling_interval_pwm;
64+
const ap_uint<BIT_WIDTH_FRACTIONAL> HALF = (scaling_interval_pwm >> 1);
5865

5966
// const WIDTH_DATA MIN_INTERVAL_VOLTAGE = -max_sym_interval;
6067
const WIDTH_DATA MAX_INTERVAL_VOLTAGE = max_sym_interval;
@@ -110,9 +117,13 @@ void voltage_modulation(hls::stream<T_FOC>& s_axis,
110117
phase_b = pwm_mod_b;
111118
phase_c = pwm_mod_c;
112119

113-
Va_out.write(pwm_mod_a);
114-
Vb_out.write(pwm_mod_b);
115-
Vc_out.write(pwm_mod_c);
120+
// Va_out.write(pwm_mod_a);
121+
// Vb_out.write(pwm_mod_b);
122+
// Vc_out.write(pwm_mod_c);
123+
pwm_packet.range((BIT_WIDTH_STEP_STREAM * 3) - 1, BIT_WIDTH_STEP_STREAM * 2) = pwm_mod_c;
124+
pwm_packet.range((BIT_WIDTH_STEP_STREAM * 2) - 1, BIT_WIDTH_STEP_STREAM) = pwm_mod_b;
125+
pwm_packet.range(BIT_WIDTH_STEP_STREAM - 1, 0) = pwm_mod_a;
126+
output_s.write(pwm_packet);
116127

117128
logger_stream_out.write(log_packet);
118129
}

‎motor_control/L1/tests/IP_VOLTAGE_MODULATION/src/main_voltage_modulation_main.cpp‎

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -26,7 +26,8 @@
2626

2727
int main(void) {
2828
hls::stream<ap_uint<BIT_WIDTH_STREAM_FOC> > input_data_stream, output_data_stream;
29-
hls::stream<ap_uint<PWM_DATA_TYPE_> > output_data_w_1, output_data_w_2, output_data_w_3;
29+
// hls::stream<ap_uint<PWM_DATA_TYPE_> > output_data_w_1, output_data_w_2, output_data_w_3;
30+
hls::stream<ap_uint<PWM_DATA_TYPE_3_PHASE> > output_s;
3031
hls::stream<ap_int<BIT_WIDTH_DATA> > input_data_w_i, output_data_w_i, voltage_in_s;
3132
hls::stream<ap_uint<BIT_WIDTH_LOG_STREAM_FOC> > log_in, log_out;
3233

@@ -36,14 +37,15 @@ int main(void) {
3637
int32_t _data_ag = 0;
3738

3839
volatile int max_sym_interval = (24 << 16), double_interval = ((24 << 16) << 1), phase_a, phase_b, phase_c;
40+
volatile int scaling_interval_pwm;
3941
volatile unsigned int mode_ = 0;
4042
input_data_stream.write(64); // last 8 bit enabled
4143
log_in.write(32); // last 8 bit enabled
42-
voltage_modulation_inst(input_data_stream, voltage_in_s, output_data_w_1, output_data_w_2, output_data_w_3, log_in,
43-
log_out, mode_, max_sym_interval, double_interval, phase_a, phase_b, phase_c);
44+
voltage_modulation_inst(input_data_stream, voltage_in_s, output_s, log_in, log_out, mode_, max_sym_interval,
45+
double_interval, scaling_interval_pwm, phase_a, phase_b, phase_c);
4446

45-
while (!output_data_w_1.empty()) {
46-
std::cout << "VAL: " << output_data_w_1.read() << std::endl;
47+
while (!output_s.empty()) {
48+
std::cout << "VAL: " << output_s.read() << std::endl;
4749
}
4850

4951
return 0;

‎motor_control/L1/tests/IP_VOLTAGE_MODULATION/src/voltage_modulation.cpp‎

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -25,38 +25,37 @@
2525

2626
void voltage_modulation_inst(hls::stream<ap_uint<BIT_WIDTH_STREAM_FOC> >& s_axis,
2727
hls::stream<ap_int<BIT_WIDTH_DATA> >& voltage_in,
28-
hls::stream<ap_uint<PWM_DATA_TYPE_> >& Va_out,
29-
hls::stream<ap_uint<PWM_DATA_TYPE_> >& Vb_out,
30-
hls::stream<ap_uint<PWM_DATA_TYPE_> >& Vc_out,
31-
// hls::stream< ap_uint< 96 > > &output_s,
28+
hls::stream<ap_uint<96> >& output_s,
3229
hls::stream<ap_uint<BIT_WIDTH_LOG_STREAM_FOC> >& logger_stream_in,
3330
hls::stream<ap_uint<BIT_WIDTH_LOG_STREAM_FOC> >& logger_stream_out,
3431
volatile unsigned int& mode,
3532
volatile int& max_sym_interval,
3633
volatile int& double_interval,
34+
volatile int& scaling_interval_pwm,
3735
volatile int& phase_a,
3836
volatile int& phase_b,
3937
volatile int& phase_c) {
4038
#pragma HLS INTERFACE mode = axis port = s_axis
4139
#pragma HLS INTERFACE mode = axis port = voltage_in
42-
#pragma HLS INTERFACE mode = axis port = Va_out
43-
#pragma HLS INTERFACE mode = axis port = Vb_out
44-
#pragma HLS INTERFACE mode = axis port = Vc_out
45-
//#pragma HLS INTERFACE mode=axis port=output_s
40+
// #pragma HLS INTERFACE mode = axis port = Va_out
41+
// #pragma HLS INTERFACE mode = axis port = Vb_out
42+
// #pragma HLS INTERFACE mode = axis port = Vc_out
43+
#pragma HLS INTERFACE mode = axis port = output_s
4644
#pragma HLS INTERFACE mode = axis port = logger_stream_in
4745
#pragma HLS INTERFACE mode = axis port = logger_stream_out
4846

4947
#pragma HLS INTERFACE mode = ap_none port = mode
5048
#pragma HLS INTERFACE mode = ap_none port = max_sym_interval
5149
#pragma HLS INTERFACE mode = ap_none port = double_interval
50+
#pragma HLS INTERFACE mode = ap_none port = scaling_interval_pwm
5251
#pragma HLS INTERFACE mode = ap_none port = phase_a
5352
#pragma HLS INTERFACE mode = ap_none port = phase_b
5453
#pragma HLS INTERFACE mode = ap_none port = phase_c
5554

5655
#pragma HLS INTERFACE mode = ap_ctrl_none port = return
5756

5857
voltage_modulation<ap_uint<BIT_WIDTH_STREAM_FOC>, ap_uint<BIT_WIDTH_LOG_STREAM_FOC>, ap_int<BIT_WIDTH_DATA>,
59-
ap_int<BIT_WIDTH_ACCUM>, ap_uint<PWM_DATA_TYPE_> >(
60-
s_axis, voltage_in, Va_out, Vb_out, Vc_out, logger_stream_in, logger_stream_out, mode, max_sym_interval,
61-
double_interval, phase_a, phase_b, phase_c);
58+
ap_int<BIT_WIDTH_ACCUM>, ap_uint<PWM_DATA_TYPE_>, ap_uint<PWM_DATA_TYPE_3_PHASE> >(
59+
s_axis, voltage_in, /*Va_out, Vb_out, Vc_out,*/ output_s, logger_stream_in, logger_stream_out, mode,
60+
max_sym_interval, double_interval, scaling_interval_pwm, phase_a, phase_b, phase_c);
6261
}

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