Merge pull request #1 from altera-fpga/24.3-rel

updating agilex5 source files for 24.3 release

Author: nithinkumark94

LICENSE

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+Copyright 2024-2025 Altera Corporation
+
+Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the “Software”), to deal in the Software without restriction, except as set forth below, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software; 
+
+If a file contained in this Software includes separate license text or a header file with license terms, those terms will supersede this agreement for purposes of that file only, all files without a separate agreement are subject to this agreement;
+
+The Software must be used solely for design and implementation on an Altera product; 
+
+You must not use the Software or devices you configure using this Software to violate any internationally recognized human right; and 
+
+THE SOFTWARE IS PROVIDED “AS IS”, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
+
+Governing Law and Jurisdiction. If you are in the Americas, U.S. and Delaware law governs all disputes arising out of or relating to this agreement without regard to conflict-of-laws principles. The state and federal courts in Wilmington, Delaware will have exclusive jurisdiction over any dispute arising out of or relating to this agreement. If you are in Europe or Africa, the laws of England and Wales govern all matters arising out of or relating to this agreement without regard to conflict-of-laws principles. The courts in England will have exclusive jurisdiction over any dispute arising out of or relating to this agreement. If you are in Asia or Australia, Singapore law governs all disputes arising out of or relating to this agreement without regard to conflict-of-laws principles. The courts in Singapore will have exclusive jurisdiction over any dispute arising out of or relating to this agreement. You and Intel consent to personal jurisdiction and venue in the courts designated for your location. If you are in China, Hong Kong law governs all disputes arising out of or relating to this agreement without regard to conflict-of-laws principles. Any dispute arising out of or relating to this agreement will be subject to arbitration by the Hong Kong International Arbitration Centre, this arbitration agreement will be governed by Hong Kong law, and the seat and location of proceedings will be Hong Kong. The current rules of the HKIAC will apply, except that the arbitration will be referred to a sole arbitrator and the proceedings will be conducted in English. The Arbitral Tribunal may only award monetary damages and may not award injunctive relief or any remedy that requires a party to license any intellectual property rights. Regardless of the above or your location, claims for misappropriation of trade secrets and breach of confidentiality obligations may also be brought in any court that has jurisdiction over the parties if the relief sought is limited to injunctive or other nonmonetary relief. The parties exclude the application of the United Nations Convention on Contracts for the International Sale of Goods (1980).

README.md

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-# agilex5e-nios-ed
-Nios V Processor example designs targeting Altera Agilex 5 Development Kits
+# Nios V Example Designs Repository
+
+This repository contains the Nios V Example designs based on Agilex™ 5 FPGA E-Series 065B Premium Development Kit
+
+Development Kit product page- https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-premium.html 
+
+The following table contains the list of Acronyms that the user may come across in the design details
+
+| Acronym | Expansion |
+| --- | ------ |
+| DMA | Direct Memory Access |
+| OCM | On-Chip Memory |
+| PIO | Parallel I/O |
+| RTOS | Real Time Operating System |
+
+There are three variants of the NiosV core:
+    
+    a. Nios V/m core - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
+    
+    b. Nios V/g core - General-Purpose Processor- High Performance (For interrupt driven baremetal and RTOS code)
+
+    c. Nios V/c core - Compact Microcontroller- Smallest (For non-interrupt driven baremetal code)
+
+
+The following table contains the list of the designs on Agilex 5 FPGA E-Series 065B Premium Development Kit
+
+| # | Nios V core | Design name | Description |
+| - | --- | ------ | ----------- |
+| 1 | Nios V/m | Nios V/m DMA OCM Design | This design demonstrates the transaction between the Nios® V processor with DMA and OCM core<br>[Design details](niosv_m/niosv_m_dma_ocm/docs/Agilex™_5_FPGA_Nios®V_m_Processor_DMA_OCM_design.pdf) |
+| 2 | Nios V/m | Nios V/m Helloworld OCM Memory test Design | Nios® V/m Processor-based Helloworld example design<br>[Design details](niosv_m/niosv_m_helloworld_ocm_mem_test/docs/Agilex™_5_FPGA_Helloworld_and_OCM_test_design_on_Nios®V_m_Processor.pdf) |
+| 3 | Nios V/m | Nios V/m PIO Design |This design demonstrates the transaction between the Nios® V processor and the Parallel Input/Output (PIO) core<br>[Design details](niosv_m/niosv_m_pio/docs/Agilex™_5_FPGA_Nios®V_m_Processor_PIO_LED_Toggle_Design.pdf) |
+| 4 | Nios V/g | Nios V/g Helloworld Design | Nios® V/g Processor-based Helloworld example design<br>[Design details](niosv_g/niosv_g_helloworld/docs/Agilex™_5_FPGA_Nios®V_g_Processor_Helloworld_Design.pdf) |
+| 5 | Nios V/g | Nios V/g OCM Memory Tese Design | Nios® V/g Processor-based OCM memory test example design<br>[Design details](niosv_g/niosv_g_ocm_mem_test/docs/Agilex™_5_FPGA_Nios®V_g_Processor_OCM_test_Design.pdf) |
+| 6 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | Nios® V/c Processor-based Helloworld and OCM memory test example design<br>[Design details](niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Agilex™_5_FPGA_Helloworld_and_OCM_test_design_on_Nios®V_c_Processor.pdf) |
+
+
+Refer to the documents in the following link for More information on the Nios V Processor core - [https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html ](https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html#introtext_1506028531_1693475107)

niosv_c/README.md

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+This directory contains the following example designs based on the Nios V/c core:
+
+    a. Nios V/c helloworld OCM design

niosv_c/niosv_c_helloworld_ocm_mem_test/README.md

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+This directory contains the following folders:
+
+1. Docs- Document capturing the details of the example design
+
+2. img- block diagram of the example design
+
+3. ready_to_test- binary files which can be programmed on the board and tested. Refer to the README.md in the sources folder for the steps
+
+4. sources- Files needed to create the design
+

niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Agilex™_5_FPGA_Helloworld_and_OCM_test_design_on_Nios®V_c_Processor.pdf

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+1. Directory structure
+2. Using existing files (sof and elf) to run on hardware
+3. Building the design from scratch
+
+    a.	Required directory structure
+
+    b.	Use of build_sof.py to compile the design
+
+    c.	Steps to create the bsp and build software sources
+
+    d.  Hardware Validation 
+    
+4. Running simulation
+
+### 1. Directory Structure:
+
+The directory structure is explained below:
+
+- hw - necessary hardware files (.qpf, .qsf, .sv, .v, .ip) of the design
+
+- sw - This folder contains software application files
+
+- scripts - This folder consists of scripts to build the design
+
+
+### 2. Using existing files to run the design on hardware
+
+- The sof and elf files required to run the design can be found in "ready_to_test" folder 
+
+- Refer the Hardware validation section (3.d) for the steps   
+
+### 3. Building the design from scratch
+
+The steps to build the project from scratch are mentioned below:
+
+a. Required directory structure
+- The top-level project folder should have directory structure as mentioned in Section 1 (Directory Structure).
+
+b. Using build_sof.py to compile the design
+- Invoke the quartus_py shell in the terminal
+
+- Run the following command in the terminal from top level project directory:     
+```    
+ quartus_py ./scripts/build_sof.py
+```
+- The quartus tool will compile the design and generate the output files
+
+c. Creating the bsp, build software sources and download elf
+- To create software app, run the following commands in the terminal:
+	
+- Clean the app build project before regenerating elf
+```	
+niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal --script=sw/bsp-update-small-driver.tcl sw/bsp/settings.bsp
+niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
+niosv-shell
+cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
+make -C sw/app/build
+elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
+```
+
+d. Hardware Validation
+- Program the generated sof file on the board
+```
+quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
+```
+- Reduce the JTAG clock frequency to 6MHz before programming the application .elf file on the board.
+```
+jtagconfig --setparam 1 JtagClock 6M
+```
+- Verify the output on the terminal by using the following command in the terminal:
+```        
+juart-terminal -d 1 -c 1 -i 0
+```
+
+### 4. Running simulation
+
+Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
+
+- Generate Testbench from Platform Designer. Generate -> Generate Testbench System
+```
+cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor
+cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
+vsim &
+source msim_setup.tcl
+ld_debug
+run -all
+```

niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png

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+<?xml version="1.0" encoding="UTF-8"?>
+<ip>
+ <presets version="12.1">
+  <preset
+     name="niosv_c_agilex5"
+     kind="intel_niosv_c"
+     version="All"
+     description="preset for niosv compact core"
+     board="Intel Agilex 5 FPGA E-Series DK A5E065BB32AES1 Premium Development Kit,Intel Agilex 5 FPGA E-Series DK A5E065BB32AES1 Premium Development Kit"
+     preset_category="NiosV">
+   <parameter name="resetOffset" value="0" />
+   <parameter name="enableECCLite" value="false" />
+   <parameter name="numGpr" value="32" />
+   <parameter name="useResetReq" value="false" />
+   <parameter name="resetSlave" value="intel_onchip_memory_0.axi_s1" />
+  </preset>
+ </presets>
+</ip>