Updating design files

Author: paddy3696

niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md

@@ -13,14 +13,14 @@
 ### Release Contents  
 
 #### Binaries
- - Prebuilt binaries are located [here](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test).
+ - Prebuilt binaries are located [here](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test).
  - The sof and elf files required to run the design can be found in "ready_to_test" folder 
  - Program the sof and download the elf file on board
 
-### Nios® V/c Helloworld OCM Memory test Design Archiecture
+### Nios® V/c Helloworld OCM Memory test Design Architecture
  This example design includes a Nios® V/c processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.
 
- ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png?raw=true)
+ ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
 
 #### Nios® V/c Processor
 - Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
@@ -54,10 +54,9 @@ Refer to [Agilex™ 5 FPGA Premium Development Kit User Guide](https://www.intel
   |0x0000_0000|1MB|On-Chip RAM|To store application|
   |0x0010_0008|8|JTAG UART|Communication between a host PC and the Nios V processor system|
   |0x0010_0000|8|System ID|Hardware configuration system ID (0x000000a5)|
-  ||||
 
 
-## User Flow 
+### User Flow 
 
  There are two ways to test the design based on use case. 
 
@@ -74,17 +73,16 @@ Refer to [Agilex™ 5 FPGA Premium Development Kit User Guide](https://www.intel
  ||Program Software Image ELF|Yes|Yes|
  |Testing|Open JTAG UART Terminal|Yes|Yes|
  ||Run simulation|Yes|Yes|
- ||||
 
 ### Environment Setup
 
 #### Tools Download and Installation
 1. Quartus Prime Pro
 
- - Download the Quartus® Prime Pro Edition software version 25.1 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
+ - Download the Quartus® Prime Pro Edition software version 25.1.1 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
  - Set up the Quartus tools in the PATH, so they are accessible without full path.
 ```console
-	export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.1/quartus/
+	export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.1.1/quartus/
 	export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH
 ```
 
@@ -111,10 +109,6 @@ cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
 make -C sw/app/build
 elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0xfffff hw/onchip_mem.hex -r4
 ```
-Note:The software can be compiled using the Ashling Visual Studio Code Extension for Altera FPGAs
-
-For information on the build process, please refer to the following document- [Ashling VSCode Extension](https://www.intel.com/content/www/us/en/docs/programmable/730783/current/ashling-visual-studio-code-extension.html)
-
 
 ### Programing 
 Note: Reduce the JTAG clock frequency to 6MHz using the following command, before programming the sof file

niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test/app.elf

@@ -1,36 +1,38 @@
-# Agilex 5 FPGA - Nios V/c Helloworld OCM Memory test Design
+# Nios® V/c Hello World and OCM test Design
 
-Nios® V/c Processor-based Helloworld and OCM memory test example design
+ Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
 
 ## Description
 
-This design prints a simple Hello World message and performs a simple OCM memory test for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
+ Nios® V/c Processor-based Helloworld example design on the Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
+
+![image](https://github.com/altera-fpga/niosv-ed/blob/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
 
-![image](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
 
 ## Project Details
 
-- **Title**: Agilex 5 FPGA- Nios V/c Helloworld OCM Memory test Design
+- **Title**: Nios® V/c Helloworld OCM Memory Test Design
 - **Source**: Github
 - **Design Support**: SCTH
 - **Family**: Agilex 5
-- **Quartus Version**: 25.1.0
+- **Quartus Version**: 25.1.1
 - **Development Kit**: Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1
 - **Device Part**: A5ED065BB32AE6SR0
 - **Design Package**: agilex5_niosv_c_helloworld_ocm_mem_test.zip
-- **Category**: Helloworld
-- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test
-- **downloadURL**:https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.1.0-v1.0/agilex5_niosv_c_helloworld_ocm_mem_test.zip
+- **Category**: Memory
+- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_c/niosv_c_helloworld_ocm_mem_test
+- **download URL**: https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.1.1-v1.0/agilex5_niosv_c_helloworld_ocm_mem_test.zip
 
 ## Documentation
 
 - **Title**: Design Document
-- **URL**:  https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md
+- **URL**:https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.1/niosv_m/niosv_m_dma_ocm/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md
 
-# Getting Started
+## Build and Run Flow
 
 Vendor: Altera
 
+Devkit Product Page: https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-premium.html
 
 1. Directory structure
 2. Using existing files (sof and elf) to run on hardware
@@ -56,6 +58,7 @@ The directory structure is explained below:
 
 - scripts - This folder consists of scripts to build the design
 
+
 ### 2. Using existing files to run the design on hardware
 
 - The sof and elf files required to run the design can be found in "ready_to_test" folder 
@@ -88,11 +91,8 @@ niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
 niosv-shell
 cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
 make -C sw/app/build
-elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0xfffff sw/app/build/onchip_mem.hex -r4
+elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0x9ffff sw/app/build/onchip_mem.hex -r4
 ```
-Note:The software can be compiled using the Ashling Visual Studio Code Extension for Altera FPGAs
-
-For information on the build process, please refer to the following document- [Ashling VSCode Extension](https://www.intel.com/content/www/us/en/docs/programmable/730783/current/ashling-visual-studio-code-extension.html)
 
 d. Hardware Validation
 - Program the generated sof file on the board
@@ -120,4 +120,4 @@ vsim &
 source msim_setup.tcl
 ld_debug
 run -all
-```
+```

niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test/top.sof

@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ip>
+ <presets version="12.1">
+  <preset
+     name="intel_niosv_c"
+     kind="intel_niosv_c"
+     version="All"
+     description=""
+     board="Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA"
+     preset_category="">
+   <parameter name="resetOffset" value="0" />
+   <parameter name="enableECCLite" value="true" />
+   <parameter name="numGpr" value="32" />
+   <parameter name="useResetReq" value="false" />
+   <parameter name="resetSlave" value="intel_onchip_memory_0.axi_s1" />
+  </preset>
+ </presets>
+</ip>

niosv_c/niosv_c_helloworld_ocm_mem_test/sources/README.md

@@ -0,0 +1,44 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<ip>
+ <presets version="12.1">
+  <preset
+     name="onchip_memory_0"
+     kind="intel_onchip_memory"
+     version="All"
+     description=""
+     board="Agilex 7 FPGA F-Series Development Kit P-Tile and E-Tile DK-DEV-AGF014EA"
+     preset_category="">
+   <parameter name="readDuringWriteMode_Mixed" value="DONT_CARE" />
+   <parameter name="lvl2OutputRegA" value="false" />
+   <parameter name="lvl2OutputRegB" value="false" />
+   <parameter name="poison_enable" value="false" />
+   <parameter name="writable" value="true" />
+   <parameter name="enPRInitMode" value="false" />
+   <parameter name="interfaceType" value="1" />
+   <parameter name="dualPort" value="0" />
+   <parameter name="clockEnable" value="false" />
+   <parameter name="ecc_check" value="false" />
+   <parameter name="ecc_encoder_bypass" value="false" />
+   <parameter name="dataWidth" value="32" />
+   <parameter name="allowInSystemMemoryContentEditor" value="false" />
+   <parameter name="initializationFileName" value="onchip_mem.hex" />
+   <parameter name="singleClockOperation" value="false" />
+   <parameter name="ecc_pipeline_reg" value="false" />
+   <parameter name="idWidth" value="2" />
+   <parameter name="blockType" value="AUTO" />
+   <parameter name="resetrequest_enabled" value="true" />
+   <parameter name="useNonDefaultInitFile" value="true" />
+   <parameter name="copyInitFile" value="false" />
+   <parameter name="lvl1OutputRegA" value="false" />
+   <parameter name="AXI_interface" value="1" />
+   <parameter name="tightly_coupled_ecc" value="false" />
+   <parameter name="lvl1OutputRegB" value="false" />
+   <parameter name="gui_debugaccess" value="false" />
+   <parameter name="memorySize" value="1048576" />
+   <parameter name="instanceID" value="NONE" />
+   <parameter name="enableDiffWidth" value="false" />
+   <parameter name="dataWidth2" value="32" />
+   <parameter name="initMemContent" value="true" />
+  </preset>
+ </presets>
+</ip>