updating rel/25.1.0 sources

Author: nithinkumark94

README.md

@@ -25,15 +25,11 @@ There are three variants of the NiosV core:
 
 The following table contains the list of the designs on Agilex 5 FPGA E-Series 065B Premium Development Kit
 
-| # | Nios V core | Design name | Description |
+| No # | Design Name Prefix (Nios V core) | Design Name Suffix (Functions) | Description |
 | - | --- | ------ | ----------- |
-| 1 | Nios V/m | Nios V/m DMA OCM Design | This design demonstrates the transaction between the Nios® V processor with DMA and OCM core<br>[Design details](niosv_m/niosv_m_dma_ocm/docs/Agilex™_5_FPGA_Nios®V_m_Processor_DMA_OCM_design.pdf) |
-| 2 | Nios V/m | Nios V/m Helloworld OCM Memory test Design | Nios® V/m Processor-based Helloworld example design<br>[Design details](niosv_m/niosv_m_helloworld_ocm_mem_test/docs/Agilex™_5_FPGA_Helloworld_and_OCM_test_design_on_Nios®V_m_Processor.pdf) |
-| 3 | Nios V/m | Nios V/m PIO Design |This design demonstrates the transaction between the Nios® V processor and the Parallel Input/Output (PIO) core<br>[Design details](niosv_m/niosv_m_pio/docs/Agilex™_5_FPGA_Nios®V_m_Processor_PIO_LED_Toggle_Design.pdf) |
-| 4 | Nios V/g | Nios V/g Helloworld Design | Nios® V/g Processor-based Helloworld example design<br>[Design details](niosv_g/niosv_g_helloworld/docs/Agilex™_5_FPGA_Nios®V_g_Processor_Helloworld_Design.pdf) |
-| 5 | Nios V/g | Nios V/g OCM Memory Tese Design | Nios® V/g Processor-based OCM memory test example design<br>[Design details](niosv_g/niosv_g_ocm_mem_test/docs/Agilex™_5_FPGA_Nios®V_g_Processor_OCM_test_Design.pdf) |
-| 6 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | Nios® V/c Processor-based Helloworld and OCM memory test example design<br>[Design details](niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Agilex™_5_FPGA_Helloworld_and_OCM_test_design_on_Nios®V_c_Processor.pdf) |
-| 7 | Nios V/m | Nios V/m Baseline Golden Hardware Reference Design (GHRD) | This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios V/m processor with basic bare minimum peripherals required for any application execution <br>[Design details](niosv_m/niosv_m_baseline_ghrd/docs/Agilex_5_FPGA_NiosV_m_Processor_baseline_ghrd_on_Agilex_5_FPGA.pdf)
+| 1 | Nios V/m | Nios V/m Baseline Golden Hardware Reference Design (GHRD) | This design demonstrates the baseline Golden Hardware Reference Design (GHRD) for a Nios V/m processor with basic bare minimum peripherals required for any application execution <br>[Design details](niosv_m/niosv_m_baseline_ghrd/docs/NiosV_m_Processor_baseline_ghrd_on_Agilex_5_FPGA.md)
+| 2 | Nios V/g | Nios V/g TinyML LiteRT | This design demonstrates the TinyML application using LiteRT for microcontrollers software with Nios® V/g processor<br>[Design details](niosv_g/tinyml_liteRT/docs/Nios_Vg_Processor_TinyML_Design_on_Agilex_5_FPGA.md) |
+| 3 | Nios V/c | Nios V/c Helloworld OCM Memory test Design | This design prints a simple Hello World message and performs a simple OCM memory test<br>[Design details](niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md) |
 
 
 Refer to the documents in the following link for More information on the Nios V Processor core - [https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html ](https://www.intel.com/content/www/us/en/support/programmable/support-resources/support-centers/nios-v-support.html#introtext_1506028531_1693475107)

niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Agilex™_5_FPGA_Helloworld_and_OCM_test_design_on_Nios®V_c_Processor.pdf

@@ -0,0 +1,146 @@
+## Introduction
+
+### Nios V/c Helloworld OCM Memory test Design Overview
+
+ This design prints a simple Hello World message and performs a simple OCM memory test for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
+
+### Prerequisites
+
+ - Agilex™ 5 FPGA E-Series 065B Premium Development Kit, ordering code DK- A5E065BB32AES1. Refer to the board documentation for more information about the development kit.
+ - Mini and Micro USB Cable. Included with the development kit.
+ - Host PC with 64 GB of RAM. Less will be fine for only exercising the binaries, and not rebuilding the design.
+ 
+### Release Contents  
+
+#### Binaries
+ - Prebuilt binaries are located [here](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test).
+ - The sof and elf files required to run the design can be found in "ready_to_test" folder 
+ - Program the sof and download the elf file on board
+
+### Nios® V/c Helloworld OCM Memory test Design Archiecture
+ This example design includes a Nios® V/c processor connected to the On Chip RAM-II, JTAG UART IP, Parallel-IO and System ID peripheral core. The objective of the design is to accomplish data transfer between the processor and soft IP peripherals.
+ 
+ ![Block Diagram](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
+
+#### Nios® V/c Processor
+- Microcontroller- Balanced (For interrupt driven baremetal and RTOS code)
+- Nios® V/c processor is highly customizable and can be tailored to meet specific application requirements, providing flexibility and scalability in embedded system designs.
+ 
+#### IP Cores
+ The following IPs are used in this Platform Designer component of the design:
+- Nios® V/c soft processor core
+
+- On Chip RAM-II
+
+- JTAG UART
+
+- Parallel-IO
+
+- System ID
+
+- Clock Bridge, Reset Controller
+
+
+### Hardware Setup
+
+Refer to [Agilex™ 5 FPGA Premium Development Kit User Guide](https://www.intel.com/content/www/us/en/docs/programmable/814550.html) to setup the hardware connection.
+
+
+### Address Map Details
+
+#### Nios V Address Map
+ |Address Offset	|Size (Bytes)	|Peripheral	| Description|
+  |-|-|-|-|
+  |0x0000_0000|1MB|On-Chip RAM|To store application|
+  |0x0010_0008|8|JTAG UART|Communication between a host PC and the Nios V processor system|
+  |0x0010_0000|8|System ID|Hardware configuration system ID (0x000000a5)|
+  ||||
+
+
+## User Flow 
+
+ There are two ways to test the design based on use case. 
+
+   <h5> User Flow 1: Testing with Prebuild Binaries.</h5>
+   
+   <h5> User Flow 2: Testing Complete Flow.</h5>
+
+ |User Flow|Description|Required for [User flow 1](#user-flow-1-testing-with-prebuild-binaries)|Required for [User flow 2](#user-flow-2-testing-complete-flow)|
+ |-|-|-|-|
+ |Environment Setup|[Tools Download and Installation](#tools-download)|Yes|Yes|
+ |Compilation|Hardware compilation|No|Yes|
+ ||Software compilation|No|Yes|    
+ |Programing|Program Hardware Binary SOF|Yes|Yes|
+ ||Program Software Image ELF|Yes|Yes|
+ |Testing|Open JTAG UART Terminal|Yes|Yes|
+ ||Run simulation|Yes|Yes|
+ ||||
+
+### Environment Setup
+
+#### Tools Download and Installation
+1. Quartus Prime Pro
+
+ - Download the Quartus® Prime Pro Edition software version 25.1 from the FPGA Software Download Center webpage of the Intel website. Follow the on-screen instructions to complete the installation process. Choose an installation directory that is relative to the Quartus® Prime Pro Edition software installation directory.
+ - Set up the Quartus tools in the PATH, so they are accessible without full path.
+```console
+	export QUARTUS_ROOTDIR=~/intelFPGA_pro/25.1/quartus/
+	export PATH=$QUARTUS_ROOTDIR/bin:$QUARTUS_ROOTDIR/linux64:$QUARTUS_ROOTDIR/../qsys/bin:$PATH
+```
+
+### Compilation 
+
+#### Hardware Compilation 
+- Invoke the `quartus_py` shell in the terminal
+- Run the following command in the terminal from top level project directory:
+ 
+```console
+quartus_py ./scripts/build_sof.py
+```
+
+ - The quartus tool will compile the design and generate the output files
+
+#### Software Compilation 
+Note: Clean the app build project before regenerating elf
+- To create software app, run the following commands in the terminal:
+```console
+niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal --script=sw/bsp-update-small-driver.tcl sw/bsp/settings.bsp
+niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
+niosv-shell
+cmake -S ./sw/app -B sw/app/build -G "Unix Makefiles"
+make -C sw/app/build
+elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0xfffff hw/onchip_mem.hex -r4
+```
+
+### Programing 
+Note: Reduce the JTAG clock frequency to 6MHz using the following command, before programming the sof file
+```console
+jtagconfig --setparam 1 JtagClock 6M
+```
+
+#### Program Hardware Binary SOF
+- Program the generated sof and then download the elf file on the board
+	
+```console
+quartus_pgm --cable=1 -m jtag -o 'p;ready_to_test/top.sof'
+```
+
+### Testing
+
+#### Open JTAG UART Terminal
+- Verify the output on the terminal by using the following command in the terminal:
+	
+```console
+juart-terminal -d 1 -c 1 -i 0 
+```
+
+#### Running simulation
+Simulation is enabled for this design where the memory is initialized with the application hex. Use the following commands to run the simulation:
+```console
+cp ./sw/app/build/onchip_mem.hex ./qsys_top_tb/qsys_top_tb/sim/mentor 
+cd hw/qsys_top_tb/qsys_top_tb/sim/mentor/
+vsim &
+source msim_setup.tcl
+ld_debug
+run -all
+```

niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md

@@ -1,3 +1,37 @@
+# Agilex 5 FPGA - Nios V/c Helloworld OCM Memory test Design
+
+Nios® V/c Processor-based Helloworld and OCM memory test example design
+
+## Description
+
+This design prints a simple Hello World message and performs a simple OCM memory test for the Agilex™ 5 FPGA E-Series 065B Premium Development Kit.
+
+![image](https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/img/hello_world_ocm.png)
+
+## Project Details
+
+- **Title**: Agilex 5 FPGA- Nios V/c Helloworld OCM Memory test Design
+- **Source**: Github
+- **Design Support**: SCTH
+- **Family**: Agilex 5
+- **Quartus Version**: 25.1.0
+- **Development Kit**: Agilex 5 FPGA E*Series 065B Premium Development Kit DK*A5E065BB32AES1
+- **Device Part**: A5ED065BB32AE6SR0
+- **Design Package**: agilex5_niosv_c_helloworld_ocm_mem_test.zip
+- **Category**: Helloworld
+- **URL**: https://github.com/altera-fpga/agilex5e-nios-ed/tree/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test
+- **downloadURL**:https://github.com/altera-fpga/agilex5e-nios-ed/releases/download/25.1-v1.0/agilex5_niosv_c_helloworld_ocm_mem_test.zi- 
+
+## Documentation
+
+- **Title**: Design Document
+- **URL**:  https://github.com/altera-fpga/agilex5e-nios-ed/blob/rel/25.1.0/niosv_c/niosv_c_helloworld_ocm_mem_test/docs/Nios_Vc_Processor_Helloworld_OCM_Memory_Test_Design_on_Agilex_5_FPGA.md
+
+# Getting Started
+
+Vendor: Altera
+
+
 1. Directory structure
 2. Using existing files (sof and elf) to run on hardware
 3. Building the design from scratch

niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test/app.elf

@@ -6,7 +6,7 @@
      kind="intel_niosv_c"
      version="All"
      description="preset for niosv compact core"
-     board="Intel Agilex 5 FPGA E-Series DK A5E065BB32AES1 Premium Development Kit,Intel Agilex 5 FPGA E-Series DK A5E065BB32AES1 Premium Development Kit"
+     board="Agilex 5 FPGA E-Series 065B Premium Development Kit DK-A5E065BB32AES1"
      preset_category="NiosV">
    <parameter name="resetOffset" value="0" />
    <parameter name="enableECCLite" value="false" />

niosv_c/niosv_c_helloworld_ocm_mem_test/ready_to_test/top.sof

@@ -1,3 +1,16 @@
+# (C) 2001-2025 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License Subscription 
+# Agreement, Altera IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
 # (C) 2001-2024 Intel Corporation. All rights reserved.
 # Your use of Intel Corporation's design tools, logic functions and other 
 # software and tools, and its AMPP partner logic functions, and any output 

niosv_c/niosv_c_helloworld_ocm_mem_test/sources/README.md

@@ -1,3 +1,16 @@
+# (C) 2001-2025 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License Subscription 
+# Agreement, Altera IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
 ####################################################################################
 # Python code to generate the .sof file from qsys and qpf tcl files
 
@@ -74,6 +87,14 @@
     logfile.write(line)
 generate_ip.wait()
 
+
+# Generate hex file
+app_creation = subprocess.Popen(["niosv-shell < scripts/niosv_app_creation.sh"], stdout=subprocess.PIPE, stderr=subprocess.STDOUT,shell= True)
+for line in app_creation.stdout:
+    logfile.write(line)
+app_creation.wait()
+
+
 # Synthesis
 quartus_sync = subprocess.Popen(["quartus_syn","{}".format(qpf_dir)], stdout=subprocess.PIPE, stderr=subprocess.STDOUT,cwd=cwd_1)
 for line in quartus_sync.stdout:

niosv_c/niosv_c_helloworld_ocm_mem_test/sources/hw/ip/presets/niosv_c_agilex5.qprs

@@ -0,0 +1,19 @@
+# (C) 2001-2025 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions and other 
+# software and tools, and its AMPP partner logic functions, and any output 
+# files from any of the foregoing (including device programming or simulation 
+# files), and any associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License Subscription 
+# Agreement, Altera IP License Agreement, or other applicable 
+# license agreement, including, without limitation, that your use is for the 
+# sole purpose of programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+
+
+niosv-bsp -c --quartus-project=hw/top.qpf --qsys=hw/qsys_top.qsys --type=hal --script=sw/bsp-update-small-driver.tcl sw/bsp/settings.bsp
+niosv-app --bsp-dir=sw/bsp --app-dir=sw/app --srcs=sw/app/main.c
+cmake -S ./sw/app -B sw/app/build
+make -C sw/app/build
+elf2hex sw/app/build/app.elf -b 0x0 -w 32 -e 0xfffff hw/onchip_mem.hex -r4
+# cp -rf hw/onchip_mem.hex hw/qsys_top_tb/qsys_top_tb/sim/mentor/