Issue
Documentation for SPI engine register map seems not matching with actual verilog source.
To Reproduce
Accessing this DATA_WIDTH register in final design gives different bit values then documentation suggests.
Expected behavior
Documentation should reflect current source state.
Desktop (please complete the following information):
- Project name = ad4134_fmc
- carrier board = custom
- Used Software = Linux
- Tool version = Vivado 2024.2,
- HDL Release version = main (8dcfec8)
Additional context
hdl/docs/regmap/adi_regmap_spi_engine.txt
Line 67:
REG
0x03
DATA_WIDTH
ENDREG
FIELD
[7:4] NUM_OF_SDI
NUM_OF_SDI
RO
Number of SDI.
It is equal with the maximum supported SDI lines in bits.
ENDFIELD
FIELD
[3:0] DATA_WIDTH
DATA_WIDTH
RO
Data width of the SDI/SDO parallel interface.
It is equal with the maximum supported transfer length in bits.
ENDFIELD
Verilog Source However:
hdl/library/spi_engine/axi_spi_engine/axi_spi_engine.v
Line 50:
parameter [15:0] DATA_WIDTH = 8,
parameter [ 7:0] NUM_OF_SDI = 1,
Line 348:
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
Thus Documentation should be:
REG
0x03
DATA_WIDTH
ENDREG
FIELD
[23:16] NUM_OF_SDI
NUM_OF_SDI
RO
Number of SDI.
It is equal with the maximum supported SDI lines in bits.
ENDFIELD
FIELD
[15:0] DATA_WIDTH
DATA_WIDTH
RO
Data width of the SDI/SDO parallel interface.
It is equal with the maximum supported transfer length in bits.
ENDFIELD
Issue
Documentation for SPI engine register map seems not matching with actual verilog source.
To Reproduce
Accessing this DATA_WIDTH register in final design gives different bit values then documentation suggests.
Expected behavior
Documentation should reflect current source state.
Desktop (please complete the following information):
Additional context
Line 67:
Verilog Source However:
Line 50:
parameter [15:0] DATA_WIDTH = 8,
parameter [ 7:0] NUM_OF_SDI = 1,
Line 348:
8'h03: up_rdata_ff <= {8'b0, NUM_OF_SDI, DATA_WIDTH};
Thus Documentation should be: