Documentation says there's a loopback mode at 'h8, but in looking at the HDL (and trying it out in practice), this doesn't seem to exist? Nor did it ever according to the git blame?
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always @(posedge dac_clk) begin |
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dac_enable <= (dac_data_sel_s == 4'h2) ? 1'b1 : 1'b0; |
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case (dac_data_sel_s) |
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4'hB: dac_data_iq_out <= full_ramp_counter; // full ramp |
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4'hA: dac_data_iq_out <= {4{full_ramp_counter[3:0]}}; // nibble ramp |
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4'h7: dac_data_iq_out <= pn15_data; |
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4'h6: dac_data_iq_out <= pn7_data; |
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4'h3: dac_data_iq_out <= 16'd0; |
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4'h2: dac_data_iq_out <= dac_data_in; |
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4'h1: dac_data_iq_out <= dac_data_sync ? dac_data_iq_out : dac_pat_data_1_s; |
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default: dac_data_iq_out <= dac_dds_data_s; |
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endcase |
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end |
Documentation says there's a loopback mode at 'h8, but in looking at the HDL (and trying it out in practice), this doesn't seem to exist? Nor did it ever according to the git blame?
hdl/library/axi_adrv9001/axi_adrv9001_tx_channel.v
Lines 164 to 176 in c8d5ea7