From eb1c30da8fc898e72183e05fc6b4e7a6ae8453c6 Mon Sep 17 00:00:00 2001 From: Christoph Jung Date: Tue, 9 Sep 2025 10:59:42 +0200 Subject: [PATCH 1/4] test riscv64 shift instructions --- tests/test_riscv64.py | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 tests/test_riscv64.py diff --git a/tests/test_riscv64.py b/tests/test_riscv64.py new file mode 100644 index 00000000..68ac639f --- /dev/null +++ b/tests/test_riscv64.py @@ -0,0 +1,37 @@ +#!/usr/bin/env python3 +import pyvex + + +def test_riscv64_sll_srl_sla(): + arch = pyvex.ARCH_RISCV64_LE + # sll x7, x10, x17 ; srl x7, x10, x17 ; sra x7, x10, x17 + opcodes = [b"\xb3\x13\x15\x01",b"\xb3\x53\x15\x01",b"\xb3\x53\x15\x41"] + for instr in opcodes: + irsb = pyvex.lift(instr, 0x100000, arch) + irsb_str = str(irsb) + assert "GET:I64(x17)" in irsb_str + assert "64to8(" in irsb_str + assert "And8(0x3f," in irsb_str # 0x3f = 63 => only use the lowest 6 bits + assert "GET:I64(x10)" in irsb_str + # Sar64, Shl64, Shr64 in irsb_str + assert "PUT(x7) =" in irsb_str + +def test_riscv64_sllw_srlw_slaw(): + arch = pyvex.ARCH_RISCV64_LE + # sllw x7, x10, x17 ; srlw x7, x10, x17 ; sraw x7, x10, x17 + opcodes = [b"\xbb\x13\x15\x01",b"\xbb\x53\x15\x01",b"\xbb\x53\x15\x41"] + for instr in opcodes: + irsb = pyvex.lift(instr, 0x100000, arch) + irsb_str = str(irsb) + assert "GET:I64(x17)" in irsb_str + assert "64to8(" in irsb_str + assert "And8(0x1f," in irsb_str # 0x1f = 31 => only use the lowest 5 bits + assert "GET:I64(x10)" in irsb_str + assert "64to32(" in irsb_str + # Sar32, Shl32, Shr32 in irsb_str + assert "PUT(x7) =" in irsb_str + + +if __name__ == "__main__": + test_riscv64_sll_srl_sla() + test_riscv64_sllw_srlw_slaw() \ No newline at end of file From a4d0710d781587e9fa24ccebce354070a90986e2 Mon Sep 17 00:00:00 2001 From: Christoph Jung Date: Wed, 10 Sep 2025 09:55:50 +0200 Subject: [PATCH 2/4] also assert the order of ir operations --- tests/test_riscv64.py | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/tests/test_riscv64.py b/tests/test_riscv64.py index 68ac639f..2ce5f8cb 100644 --- a/tests/test_riscv64.py +++ b/tests/test_riscv64.py @@ -8,13 +8,13 @@ def test_riscv64_sll_srl_sla(): opcodes = [b"\xb3\x13\x15\x01",b"\xb3\x53\x15\x01",b"\xb3\x53\x15\x41"] for instr in opcodes: irsb = pyvex.lift(instr, 0x100000, arch) - irsb_str = str(irsb) - assert "GET:I64(x17)" in irsb_str - assert "64to8(" in irsb_str - assert "And8(0x3f," in irsb_str # 0x3f = 63 => only use the lowest 6 bits - assert "GET:I64(x10)" in irsb_str + irsb_lines = str(irsb).splitlines() + assert "GET:I64(x17)" in irsb_lines[4] + assert "64to8(" in irsb_lines[5] + assert "And8(0x3f," in irsb_lines[6] # 0x3f = 63 => only use the lowest 6 bits + assert "GET:I64(x10)" in irsb_lines[7] # Sar64, Shl64, Shr64 in irsb_str - assert "PUT(x7) =" in irsb_str + assert "PUT(x7) =" in irsb_lines[9] def test_riscv64_sllw_srlw_slaw(): arch = pyvex.ARCH_RISCV64_LE @@ -22,14 +22,15 @@ def test_riscv64_sllw_srlw_slaw(): opcodes = [b"\xbb\x13\x15\x01",b"\xbb\x53\x15\x01",b"\xbb\x53\x15\x41"] for instr in opcodes: irsb = pyvex.lift(instr, 0x100000, arch) - irsb_str = str(irsb) - assert "GET:I64(x17)" in irsb_str - assert "64to8(" in irsb_str - assert "And8(0x1f," in irsb_str # 0x1f = 31 => only use the lowest 5 bits - assert "GET:I64(x10)" in irsb_str - assert "64to32(" in irsb_str + irsb_lines = str(irsb).splitlines() + assert "GET:I64(x17)" in irsb_lines[4] + assert "64to8(" in irsb_lines[5] + assert "And8(0x1f," in irsb_lines[6] # 0x1f = 31 => only use the lowest 5 bits + assert "GET:I64(x10)" in irsb_lines[7] + assert "64to32(" in irsb_lines[8] # Sar32, Shl32, Shr32 in irsb_str - assert "PUT(x7) =" in irsb_str + assert "32Sto64(" in irsb_lines[10] + assert "PUT(x7) =" in irsb_lines[11] if __name__ == "__main__": From 8859c30dbac7ba5c75dc0a37a0ec395f145f6469 Mon Sep 17 00:00:00 2001 From: "pre-commit-ci[bot]" <66853113+pre-commit-ci[bot]@users.noreply.github.com> Date: Wed, 10 Sep 2025 08:07:43 +0000 Subject: [PATCH 3/4] [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --- tests/test_riscv64.py | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/tests/test_riscv64.py b/tests/test_riscv64.py index 2ce5f8cb..ceb2e660 100644 --- a/tests/test_riscv64.py +++ b/tests/test_riscv64.py @@ -5,27 +5,28 @@ def test_riscv64_sll_srl_sla(): arch = pyvex.ARCH_RISCV64_LE # sll x7, x10, x17 ; srl x7, x10, x17 ; sra x7, x10, x17 - opcodes = [b"\xb3\x13\x15\x01",b"\xb3\x53\x15\x01",b"\xb3\x53\x15\x41"] - for instr in opcodes: + opcodes = [b"\xb3\x13\x15\x01", b"\xb3\x53\x15\x01", b"\xb3\x53\x15\x41"] + for instr in opcodes: irsb = pyvex.lift(instr, 0x100000, arch) irsb_lines = str(irsb).splitlines() assert "GET:I64(x17)" in irsb_lines[4] assert "64to8(" in irsb_lines[5] - assert "And8(0x3f," in irsb_lines[6] # 0x3f = 63 => only use the lowest 6 bits + assert "And8(0x3f," in irsb_lines[6] # 0x3f = 63 => only use the lowest 6 bits assert "GET:I64(x10)" in irsb_lines[7] # Sar64, Shl64, Shr64 in irsb_str assert "PUT(x7) =" in irsb_lines[9] + def test_riscv64_sllw_srlw_slaw(): arch = pyvex.ARCH_RISCV64_LE # sllw x7, x10, x17 ; srlw x7, x10, x17 ; sraw x7, x10, x17 - opcodes = [b"\xbb\x13\x15\x01",b"\xbb\x53\x15\x01",b"\xbb\x53\x15\x41"] - for instr in opcodes: + opcodes = [b"\xbb\x13\x15\x01", b"\xbb\x53\x15\x01", b"\xbb\x53\x15\x41"] + for instr in opcodes: irsb = pyvex.lift(instr, 0x100000, arch) irsb_lines = str(irsb).splitlines() assert "GET:I64(x17)" in irsb_lines[4] assert "64to8(" in irsb_lines[5] - assert "And8(0x1f," in irsb_lines[6] # 0x1f = 31 => only use the lowest 5 bits + assert "And8(0x1f," in irsb_lines[6] # 0x1f = 31 => only use the lowest 5 bits assert "GET:I64(x10)" in irsb_lines[7] assert "64to32(" in irsb_lines[8] # Sar32, Shl32, Shr32 in irsb_str @@ -35,4 +36,4 @@ def test_riscv64_sllw_srlw_slaw(): if __name__ == "__main__": test_riscv64_sll_srl_sla() - test_riscv64_sllw_srlw_slaw() \ No newline at end of file + test_riscv64_sllw_srlw_slaw() From 05a7f3ee72572f9b1bc00cdde96b91acb88f6e5f Mon Sep 17 00:00:00 2001 From: Audrey Dutcher Date: Mon, 29 Sep 2025 13:44:49 -0700 Subject: [PATCH 4/4] bump vex --- vex | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vex b/vex index 421bf0d9..61f23734 160000 --- a/vex +++ b/vex @@ -1 +1 @@ -Subproject commit 421bf0d9ec800df09fe4f8d90a8c13a0c63325e3 +Subproject commit 61f2373464af0a8df436bd88be36bdf129c2032f