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hw/drivers/i2s: Fix setting for bypass mode
With this change when bypass is enabled ratio between MSCK and BCLK is computed when needed. Previously user could prepare mck_setup and ratio values but now it's done automatically Signed-off-by: Jerzy Kasenberg <[email protected]>
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hw/drivers/i2s/i2s_nrfx/src/i2s_nrfx.c

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Original file line numberDiff line numberDiff line change
@@ -218,6 +218,48 @@ static const struct i2s_clock_cfg mck_for_24_bit_samples[] = {
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{ NRF_I2S_MCK_32MDIV15, NRF_I2S_RATIO_48X} /* 48000: 44444.444 LRCK error -7.4% */
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};
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static void
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set_mck_setup_for_bypass(nrfx_i2s_config_t *cfg, uint32_t sample_rate)
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{
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#if NRF_I2S_HAS_CLKCONFIG
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static const struct {
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uint16_t ratio_val;
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nrf_i2s_ratio_t ratio_enum;
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} ratios[] = {
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{ 32, NRF_I2S_RATIO_32X },
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{ 48, NRF_I2S_RATIO_48X },
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{ 64, NRF_I2S_RATIO_64X },
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{ 96, NRF_I2S_RATIO_96X },
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{ 128, NRF_I2S_RATIO_128X },
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{ 192, NRF_I2S_RATIO_192X },
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{ 256, NRF_I2S_RATIO_256X },
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{ 384, NRF_I2S_RATIO_384X },
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{ 512, NRF_I2S_RATIO_512X }
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};
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uint32_t mclk;
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uint16_t mclk_div;
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size_t i;
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if (cfg->enable_bypass) {
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mclk = cfg->clksrc == NRF_I2S_CLKSRC_PCLK32M ? 32000000UL : 12288000UL;
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mclk_div = mclk / sample_rate;
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for (i = 0; i < ARRAY_SIZE(ratios); i++) {
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if (mclk_div == ratios[i].ratio_val) {
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/* Ratio for bit clock */
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cfg->ratio = ratios[i].ratio_enum;
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break;
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}
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}
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assert(i < ARRAY_SIZE(ratios));
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/* Anything, needed by NRFX */
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cfg->mck_setup = NRF_I2S_MCK_32MDIV8;
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}
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#endif
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}
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static void
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i2s_nrfx_select_clock_cfg(nrfx_i2s_config_t *cfg, uint32_t sample_rate)
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{
@@ -227,6 +269,9 @@ i2s_nrfx_select_clock_cfg(nrfx_i2s_config_t *cfg, uint32_t sample_rate)
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float src_frq;
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uint32_t ratio;
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uint32_t mck;
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set_mck_setup_for_bypass(cfg, sample_rate);
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if (cfg->clksrc == I2S_CONFIG_CLKCONFIG_CLKSRC_ACLK) {
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NRF_CLOCK->TASKS_HFCLKAUDIOSTOP = 1;
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if (88200 / sample_rate * sample_rate == 88200) {

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