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terryzbaiterryzbai
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wip: clean up header file and minor fixes
Signed-off-by: Terry Bai <tianyi.bai@unsw.edu.au>
1 parent 3e27cd9 commit 889d272

2 files changed

Lines changed: 106 additions & 106 deletions

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‎drivers/network/ixgbe/ethernet.c‎

Lines changed: 18 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -26,15 +26,16 @@ __attribute__((__section__(".net_driver_config"))) net_driver_config_t config;
2626

2727
#define RX_IRQ_VECTOR 0
2828
#define TX_IRQ_VECTOR 1
29+
#define IRQ_CH 16
2930

3031
// Minimum inter-interrupt interval specified in 2.048 us units
3132
// at 1 GbE and 10 GbE link
3233
#define IRQ_INTERVAL 40
3334

34-
const uint64_t hw_rx_ring_paddr = 0x10000000;
35-
const uint64_t hw_rx_ring_vaddr = 0x2400000;
36-
const uint64_t hw_tx_ring_paddr = 0x10004000;
37-
const uint64_t hw_tx_ring_vaddr = 0x2404000;
35+
const uintptr_t hw_rx_ring_paddr = 0x10000000;
36+
const uintptr_t hw_rx_ring_vaddr = 0x2400000;
37+
const uintptr_t hw_tx_ring_paddr = 0x10004000;
38+
const uintptr_t hw_tx_ring_vaddr = 0x2404000;
3839

3940
#define NUM_TX_DESCS 512llu
4041
#define NUM_RX_DESCS 512llu
@@ -125,7 +126,7 @@ void print_mac_addr()
125126
mac[4] = high & 0xff;
126127
mac[5] = high >> 8 & 0xff;
127128

128-
sddf_dprintf("mac - %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
129+
LOG_DRIVER("mac - %02x:%02x:%02x:%02x:%02x:%02x\n", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
129130
}
130131

131132
uint32_t get_link_speed(void)
@@ -240,7 +241,8 @@ void tx_provide(void)
240241
| IXGBE_ADVTXD_DCMD_DEXT | IXGBE_ADVTXD_DTYP_DATA | (uint32_t)buffer.len;
241242
desc->read.olinfo_status = ((uint32_t)buffer.len << IXGBE_ADVTXD_PAYLEN_SHIFT);
242243

243-
// Section 7.2.3.2.3 - same reason with Rx descriptors to have a local copy
244+
// Section 7.2.3.2.3 - We need a local copy becasue TX descriptor
245+
// does not contain the address at write-back phase.
244246
device.tx_descr_mdata[device.tx_tail] = buffer;
245247

246248
device.tx_tail = (device.tx_tail + 1) % NUM_TX_DESCS;
@@ -304,7 +306,6 @@ void init(void)
304306
eth_regs->ctrl = IXGBE_CTRL_PCIE_MASTER_DISABLE;
305307
while (eth_regs->status & IXGBE_STATUS_PCIE_MASTER_STATUS);
306308

307-
308309
// Global Reset and General Configuration, see Section 4.6.3.2
309310
eth_regs->ctrl |= IXGBE_CTRL_RST;
310311
while ((eth_regs->ctrl & IXGBE_CTRL_RST_MASK) != 0);
@@ -326,13 +327,8 @@ void init_1(void)
326327
while ((eth_regs->rdrxctl & IXGBE_RDRXCTL_DMAIDONE) != IXGBE_RDRXCTL_DMAIDONE);
327328

328329
// section 4.6.4 - initialize link (auto negotiation)
329-
// link auto-configuration register should already be set correctly
330-
331-
// negotiate link
332-
/* datasheet wants us to wait for the link here, but we can continue and wait afterwards */
333-
334-
// section 4.6.5 - statistical counters
335-
// Initialise the Rx statistic registers.
330+
// link auto-configuration register should already be set correctly
331+
// datasheet wants us to wait for the link here, but we can continue and wait afterwards
336332

337333
// section 4.6.5 - statistical counters
338334
// Initialise the Rx statistic registers.
@@ -367,8 +363,8 @@ void init_1(void)
367363
// use only queue 0
368364
eth_regs->rx_dma[0].srrctl &= ~IXGBE_SRRCTL_DESCTYPE_MASK;
369365
eth_regs->rx_dma[0].srrctl |= IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF | IXGBE_SRRCTL_DROP_EN;
370-
eth_regs->rx_dma[0].rdbal = hw_rx_ring_paddr & 0xFFFFFFFFull;
371-
eth_regs->rx_dma[0].rdbah = hw_rx_ring_paddr >> 32;
366+
eth_regs->rx_dma[0].rdbal = (uint32_t)(hw_rx_ring_paddr & 0xFFFFFFFFull);
367+
eth_regs->rx_dma[0].rdbah = (uint32_t)(hw_rx_ring_paddr >> 32);
372368
eth_regs->rx_dma[0].rdlen = NUM_RX_DESCS * sizeof(ixgbe_adv_rx_desc_t);
373369
eth_regs->rx_dma[0].rdh = 0;
374370
eth_regs->rx_dma[0].rdt = 0;
@@ -391,8 +387,8 @@ void init_1(void)
391387
eth_regs->txpbthresh[i] = 0;
392388
}
393389

394-
eth_regs->tx_dma[0].tdbal = hw_tx_ring_paddr & 0xFFFFFFFFull;
395-
eth_regs->tx_dma[0].tdbah = hw_tx_ring_paddr >> 32;
390+
eth_regs->tx_dma[0].tdbal = (uint32_t)(hw_tx_ring_paddr & 0xFFFFFFFFull);
391+
eth_regs->tx_dma[0].tdbah = (uint32_t)(hw_tx_ring_paddr >> 32);
396392
eth_regs->tx_dma[0].tdh = 0;
397393
eth_regs->tx_dma[0].tdt = 0;
398394

@@ -407,7 +403,7 @@ void init_1(void)
407403

408404
// final step: enable DMA
409405
eth_regs->dmatxctl = IXGBE_DMATXCTL_TE;
410-
eth_regs->tx_dma[0].txdctl = IXGBE_TXDCTL_ENABLE;
406+
eth_regs->tx_dma[0].txdctl |= IXGBE_TXDCTL_ENABLE;
411407
while ((eth_regs->tx_dma[0].txdctl & IXGBE_TXDCTL_ENABLE) == 0);
412408
}
413409

@@ -439,7 +435,7 @@ void init_3(void)
439435

440436
enable_interrupts();
441437

442-
sddf_dprintf("Finish NIC reset\n");
438+
LOG_DRIVER("Finish NIC reset\n");
443439
device.init_stage = 4;
444440
}
445441

@@ -453,10 +449,10 @@ void notified(microkit_channel ch)
453449
} else if (device.init_stage == 2) {
454450
init_3();
455451
}
456-
} else if (device.init_stage != 4 && ch == 16) {
452+
} else if (device.init_stage != 4 && ch == IRQ_CH) {
457453
sddf_deferred_irq_ack(ch);
458454
} else if (device.init_stage == 4) {
459-
if (ch == 16) {
455+
if (ch == IRQ_CH) {
460456
// read-to-clear
461457
uint32_t cause = eth_regs->eicr;
462458
if (cause & BIT(TX_IRQ_VECTOR)) {

‎drivers/network/ixgbe/ethernet.h‎

Lines changed: 88 additions & 84 deletions
Original file line numberDiff line numberDiff line change
@@ -6,117 +6,121 @@
66
* https://www.intel.com/content/www/us/en/content-details/333369/intel-ethernet-controller-x550-datasheet.html
77
*/
88
#pragma once
9-
109
#include <stdint.h>
1110
#include <sddf/util/printf.h>
1211

13-
#define PCIE_CONFIG_BASE 0x3000000lu
14-
#define DEVICE_BASE 0x2000000lu
15-
#define DEVICE_MSIX_TABLE 0x4000000lu
12+
// #define DEBUG_DRIVER
13+
14+
#ifdef DEBUG_DRIVER
15+
#define LOG_DRIVER(...) do{ sddf_dprintf("ETH DRIVER|INFO: "); sddf_dprintf(__VA_ARGS__); }while(0)
16+
#else
17+
#define LOG_DRIVER(...) do{}while(0)
18+
#endif
1619

17-
const uint64_t IXGBE_CTRL_LNK_RST = 0x00000008; /* Link Reset. Resets everything. */
18-
const uint64_t IXGBE_CTRL_RST = 0x04000000; /* Reset (SW) */
19-
const uint64_t IXGBE_CTRL_RST_MASK = IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST;
20-
const uint64_t IXGBE_CTRL_PCIE_MASTER_DISABLE = 1 << 2;
20+
#define LOG_DRIVER_ERR(...) do{ sddf_printf("ETH DRIVER|ERROR: "); sddf_printf(__VA_ARGS__); }while(0)
2121

22-
const uint64_t IXGBE_STATUS_PCIE_MASTER_STATUS = 1 << 19;
23-
const uint64_t IXGBE_CTRL_EXT_DRV_LOAD = 1 << 28;
22+
#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */
23+
#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */
24+
#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST)
25+
#define IXGBE_CTRL_PCIE_MASTER_DISABLE (1 << 2)
2426

25-
const uint64_t IXGBE_EEC_ARD = 0x00000200; /* EEPROM Auto Read Done */
26-
const uint64_t IXGBE_RDRXCTL_DMAIDONE = 0x00000008; /* DMA init cycle done */
27+
#define IXGBE_STATUS_PCIE_MASTER_STATUS (1 << 19)
28+
#define IXGBE_CTRL_EXT_DRV_LOAD (1 << 28)
2729

28-
const uint64_t IXGBE_AUTOC_LMS_SHIFT = 13;
29-
const uint64_t IXGBE_AUTOC_LMS_MASK = 0x7 << IXGBE_AUTOC_LMS_SHIFT;
30-
const uint64_t IXGBE_AUTOC_LMS_10G_SERIAL = 0x3 << IXGBE_AUTOC_LMS_SHIFT;
31-
const uint64_t IXGBE_AUTOC_10G_PMA_PMD_MASK = 0x00000180;
32-
const uint64_t IXGBE_AUTOC_10G_PMA_PMD_SHIFT = 7;
33-
const uint64_t IXGBE_AUTOC_10G_XAUI = 0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT;
34-
const uint64_t IXGBE_AUTOC_AN_RESTART = 0x00001000;
30+
#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */
31+
#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */
3532

36-
const uint64_t IXGBE_RXCTRL_RXEN = 0x00000001; /* Enable Receiver */
33+
#define IXGBE_AUTOC_LMS_SHIFT 13
34+
#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT)
35+
#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT)
36+
#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180
37+
#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7
38+
#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT)
39+
#define IXGBE_AUTOC_AN_RESTART 0x00001000
3740

38-
const uint64_t IXGBE_RXPBSIZE_128KB = 0x00020000; /* 128KB Packet Buffer */
41+
#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */
3942

40-
const uint64_t IXGBE_HLREG0_RXCRCSTRP = 0x00000002; /* bit 1 */
41-
const uint64_t IXGBE_HLREG0_LPBK = 1 << 15;
42-
const uint64_t IXGBE_RDRXCTL_CRCSTRIP = 0x00000002; /* CRC Strip */
43+
#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */
4344

44-
const uint64_t IXGBE_FCTRL_BAM = 0x00000400; /* Broadcast Accept Mode */
45+
#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */
46+
#define IXGBE_HLREG0_LPBK (1 << 15)
47+
#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */
4548

46-
const uint64_t IXGBE_CTRL_EXT_NS_DIS = 0x00010000; /* No Snoop disable */
49+
#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */
4750

48-
const uint64_t IXGBE_HLREG0_TXCRCEN = 0x00000001; /* bit 0 */
49-
const uint64_t IXGBE_HLREG0_TXPADEN = 0x00000400; /* bit 10 */
51+
#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */
5052

51-
const uint64_t IXGBE_TXPBSIZE_40KB = 0x0000A000; /* 40KB Packet Buffer */
52-
const uint64_t IXGBE_RTTDCS_ARBDIS = 0x00000040; /* DCB arbiter disable */
53+
#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */
54+
#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */
5355

54-
const uint64_t IXGBE_DMATXCTL_TE = 0x1; /* Transmit Enable */
56+
#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */
57+
#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */
5558

56-
const uint64_t IXGBE_RXDCTL_ENABLE = 0x02000000; /* Ena specific Rx Queue, bit 25 */
57-
const uint64_t IXGBE_TXDCTL_ENABLE = 0x02000000; /* Ena specific Tx Queue, bit 25 */
58-
const uint64_t IXGBE_RSCINT_RSCEN = 0x00000001; /* RSC Enable */
59-
const uint64_t IXGBE_RSCCTL_RSCEN = 0x00000001; /* RSC Enable */
59+
#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */
60+
#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue, bit 25 */
61+
#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue, bit 25 */
62+
#define IXGBE_RSCINT_RSCEN 0x00000001 /* RSC Enable */
63+
#define IXGBE_RSCCTL_RSCEN 0x00000001 /* RSC Enable */
6064
/* RSCCTL bit 3:2 Maximum descriptors per large receive */
61-
const uint64_t IXGBE_RSCCTL_MAXDESC_1 = 0x0; /* 00b = Maximum Descriptors 1 */
62-
const uint64_t IXGBE_RSCCTL_MAXDESC_4 = 0x4; /* 01b = Maximum Descriptors 4 */
63-
const uint64_t IXGBE_RSCCTL_MAXDESC_8 = 0x8; /* 10b = Maximum Descriptors 8 */
64-
const uint64_t IXGBE_RSCCTL_MAXDESC_16 = 0xc; /* 11b = Maximum Descriptors 16 */
65-
const uint64_t IXGBE_EITR_ITR_INTERVAL = 0x00000008; /* bit 3 */
65+
#define IXGBE_RSCCTL_MAXDESC_1 0x0 /* 00b = Maximum Descriptors 1 */
66+
#define IXGBE_RSCCTL_MAXDESC_4 0x4 /* 01b = Maximum Descriptors 4 */
67+
#define IXGBE_RSCCTL_MAXDESC_8 0x8 /* 10b = Maximum Descriptors 8 */
68+
#define IXGBE_RSCCTL_MAXDESC_16 0xc /* 11b = Maximum Descriptors 16 */
69+
#define IXGBE_EITR_ITR_INTERVAL 0x00000008 /* bit 3 */
6670

67-
const uint64_t IXGBE_FCTRL_MPE = 0x00000100; /* Multicast Promiscuous Ena*/
68-
const uint64_t IXGBE_FCTRL_UPE = 0x00000200; /* Unicast Promiscuous Ena */
71+
#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/
72+
#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */
6973

70-
const uint64_t IXGBE_LINKS_UP = 0x40000000;
71-
const uint64_t IXGBE_LINKS_SPEED_82599 = 0x30000000;
72-
const uint64_t IXGBE_LINKS_SPEED_100_82599 = 0x10000000;
73-
const uint64_t IXGBE_LINKS_SPEED_1G_82599 = 0x20000000;
74-
const uint64_t IXGBE_LINKS_SPEED_10G_82599 = 0x30000000;
74+
#define IXGBE_LINKS_UP 0x40000000
75+
#define IXGBE_LINKS_SPEED_82599 0x30000000
76+
#define IXGBE_LINKS_SPEED_100_82599 0x10000000
77+
#define IXGBE_LINKS_SPEED_1G_82599 0x20000000
78+
#define IXGBE_LINKS_SPEED_10G_82599 0x30000000
7579

76-
const uint32_t IXGBE_IVAR_ALLOC_VAL = 0x80; /* Interrupt Allocation valid */
77-
const uint64_t IXGBE_EICR_RTX_QUEUE = 0x0000FFFF; /* RTx Queue Interrupt */
80+
#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */
81+
#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */
7882

7983
/* Interrupt clear mask */
80-
const uint64_t IXGBE_IRQ_CLEAR_MASK = 0xFFFFFFFF;
81-
82-
const uint64_t IXGBE_GPIE_MSIX_MODE = 0x00000010; /* MSI-X mode */
83-
const uint64_t IXGBE_GPIE_OCD = 0x00000020; /* Other Clear Disable */
84-
const uint64_t IXGBE_GPIE_EIMEN = 0x00000040; /* Immediate Interrupt Enable */
85-
const uint64_t IXGBE_GPIE_EIAME = 0x40000000;
86-
const uint64_t IXGBE_GPIE_PBA_SUPPORT = 0x80000000;
87-
88-
const uint64_t SRRCTL_BSIZEHEADER_MASK = 0b11111100000000;
89-
const uint64_t IXGBE_SRRCTL_DESCTYPE_MASK = 0x0E000000;
90-
const uint64_t IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF = 0x02000000;
91-
const uint64_t IXGBE_SRRCTL_DROP_EN = 0x10000000;
92-
93-
const uint32_t IXGBE_RXD_STAT_DD = 0x01; /* Descriptor Done */
94-
const uint32_t IXGBE_RXD_STAT_EOP = 0x02; /* End of Packet */
95-
const uint32_t IXGBE_RXDADV_STAT_DD = IXGBE_RXD_STAT_DD; /* Done */
96-
const uint32_t IXGBE_RXDADV_STAT_EOP = IXGBE_RXD_STAT_EOP; /* End of Packet */
97-
98-
const uint32_t IXGBE_ADVTXD_PAYLEN_SHIFT = 14; /* Adv desc PAYLEN shift */
99-
const uint32_t IXGBE_TXD_CMD_EOP = 0x01000000; /* End of Packet */
100-
const uint32_t IXGBE_ADVTXD_DCMD_EOP = IXGBE_TXD_CMD_EOP; /* End of Packet */
101-
const uint32_t IXGBE_TXD_CMD_RS = 0x08000000; /* Report Status */
102-
const uint32_t IXGBE_ADVTXD_DCMD_RS = IXGBE_TXD_CMD_RS; /* Report Status */
103-
const uint32_t IXGBE_TXD_CMD_IFCS = 0x02000000; /* Insert FCS (Ethernet CRC) */
104-
const uint32_t IXGBE_ADVTXD_DCMD_IFCS = IXGBE_TXD_CMD_IFCS; /* Insert FCS */
105-
const uint32_t IXGBE_TXD_CMD_DEXT = 0x20000000; /* Desc extension (0 = legacy) */
106-
const uint32_t IXGBE_ADVTXD_DTYP_DATA = 0x00300000; /* Adv Data Descriptor */
107-
const uint32_t IXGBE_ADVTXD_DCMD_DEXT = IXGBE_TXD_CMD_DEXT; /* Desc ext 1=Adv */
108-
const uint32_t IXGBE_TXD_STAT_DD = 0x00000001; /* Descriptor Done */
109-
const uint32_t IXGBE_ADVTXD_STAT_DD = IXGBE_TXD_STAT_DD; /* Descriptor Done */
110-
111-
112-
#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB, section 7.2.1.2.2 */
84+
#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF
85+
86+
#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */
87+
#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */
88+
#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */
89+
#define IXGBE_GPIE_EIAME 0x40000000
90+
#define IXGBE_GPIE_PBA_SUPPORT 0x80000000
91+
92+
#define SRRCTL_BSIZEHEADER_MASK 0x3F00
93+
#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000
94+
#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
95+
#define IXGBE_SRRCTL_DROP_EN 0x10000000
96+
97+
#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */
98+
#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */
99+
#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */
100+
#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */
101+
102+
#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
103+
#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */
104+
#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */
105+
#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */
106+
#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */
107+
#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
108+
#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */
109+
#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */
110+
#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */
111+
#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */
112+
#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */
113+
#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */
114+
115+
116+
#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB, section 7.2.1.2.2 */
113117

114118
// bit 15:0, Receive/Transmit Queue Interrupts, activated on receive/transmit
115119
// events.The mapping of queue to the RTxQ bits is done by the IVAR registers
116-
const uint64_t IXGBE_EICR_RTXQ_BASE = 1;
120+
#define IXGBE_EICR_RTXQ_BASE 1
117121
// Missed packet interrupt is activated for each received packet that
118122
// overflows the Rx packet buffer (overrun)
119-
const uint64_t IXGBE_EICR_RX_MISS = 1 << 17;
123+
#define IXGBE_EICR_RX_MISS (1 << 17)
120124

121125
typedef struct {
122126
uint64_t pkt_addr; // Packet buffer address

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