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feat(armv8r): handle different timer init cases
Signed-off-by: Jose Martins <[email protected]>
1 parent b90e2c3 commit 029dd5e

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7 files changed

+246
-16
lines changed

7 files changed

+246
-16
lines changed

‎ci‎

‎src/arch/armv8/armv8-r/vmm.c‎

Lines changed: 28 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -15,24 +15,37 @@ static uint32_t timer_freq = 0;
1515
void vmm_arch_profile_init()
1616
{
1717
if (cpu_is_master()) {
18-
/**
19-
* Since there is no firmware in cortex-r platforms, we need to initialize the system
20-
* counter.
21-
*/
22-
volatile struct generic_timer_cntctrl* timer_ctl;
23-
timer_ctl = (struct generic_timer_cntctrl*)mem_alloc_map_dev(&cpu()->as, SEC_HYP_PRIVATE,
24-
platform.arch.generic_timer.base_addr, platform.arch.generic_timer.base_addr,
25-
sizeof(struct generic_timer_cntctrl));
26-
27-
timer_ctl->CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN;
28-
fence_ord_write();
29-
30-
timer_freq = timer_ctl->CNTDIF0;
31-
32-
mem_unmap(&cpu()->as, (vaddr_t)timer_ctl, sizeof(struct generic_timer_cntctrl), false);
18+
unsigned long cur_cntfrq = sysreg_cntfrq_el0_read();
19+
if (cur_cntfrq != 0UL) {
20+
timer_freq = (uint32_t)cur_cntfrq;
21+
} else if (platform.arch.generic_timer.fixed_freq != 0) {
22+
timer_freq = (uint32_t)platform.arch.generic_timer.fixed_freq;
23+
} else {
24+
25+
if (platform.arch.generic_timer.base_addr == 0) {
26+
ERROR("generic timer base_addr undefined; cannot init system counter");
27+
}
28+
29+
volatile struct generic_timer_cntctrl* timer_ctl;
30+
timer_ctl = (struct generic_timer_cntctrl*)mem_alloc_map_dev(&cpu()->as,
31+
SEC_HYP_PRIVATE, platform.arch.generic_timer.base_addr,
32+
platform.arch.generic_timer.base_addr, sizeof(struct generic_timer_cntctrl));
33+
34+
timer_ctl->CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN;
35+
fence_ord_write();
36+
37+
timer_freq = (uint32_t)timer_ctl->CNTDIF0;
38+
39+
mem_unmap(&cpu()->as, (vaddr_t)timer_ctl, sizeof(struct generic_timer_cntctrl),
40+
false);
41+
}
3342
}
3443

3544
cpu_sync_barrier(&cpu_glb_sync);
3645

46+
/* Program CNTFRQ_EL0 and verify. */
3747
sysreg_cntfrq_el0_write(timer_freq);
48+
if (sysreg_cntfrq_el0_read() != (unsigned long)timer_freq) {
49+
ERROR("failed to program CNTFRQ_EL0 to %u Hz", timer_freq);
50+
}
3851
}

‎src/arch/armv8/armv8-r/vmm_BACKUP_2363469.c‎

Lines changed: 75 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,75 @@
1+
/**
2+
* SPDX-License-Identifier: Apache-2.0
3+
* Copyright (c) Bao Project and Contributors. All rights reserved.
4+
*/
5+
6+
#include <bao.h>
7+
#include <vmm.h>
8+
#include <platform.h>
9+
#include <arch/generic_timer.h>
10+
#include <cpu.h>
11+
#include <fences.h>
12+
13+
static uint32_t timer_freq = 0;
14+
15+
void vmm_arch_profile_init()
16+
{
17+
if (cpu_is_master()) {
18+
unsigned long cur_cntfrq = sysreg_cntfrq_el0_read();
19+
if (cur_cntfrq != 0UL) {
20+
timer_freq = (uint32_t)cur_cntfrq;
21+
<<<<<<< HEAD
22+
} else if (platform.arch.generic_timer.fixed_freq != 0)
23+
timer_freq = (uint32_t)PLAT_GENERIC_TIMER_FREQ_HZ;
24+
} else {
25+
26+
if (platform.arch.generic_timer.base_addr == 0) {
27+
ERROR("generic timer base_addr undefined; cannot init system counter");
28+
}
29+
30+
volatile struct generic_timer_cntctrl* timer_ctl;
31+
timer_ctl = (struct generic_timer_cntctrl*)mem_alloc_map_dev(&cpu()->as,
32+
SEC_HYP_PRIVATE, platform.arch.generic_timer.base_addr,
33+
platform.arch.generic_timer.base_addr, sizeof(struct generic_timer_cntctrl));
34+
35+
timer_ctl->CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN;
36+
fence_ord_write();
37+
38+
timer_freq = (uint32_t)timer_ctl->CNTDIF0;
39+
40+
mem_unmap(&cpu()->as, (vaddr_t)timer_ctl, sizeof(struct generic_timer_cntctrl),
41+
false);
42+
=======
43+
} else {
44+
#ifdef PLAT_GENERIC_TIMER_FREQ_HZ
45+
timer_freq = (uint32_t)PLAT_GENERIC_TIMER_FREQ_HZ;
46+
#else
47+
if (platform.arch.generic_timer.base_addr == 0) {
48+
ERROR("generic timer base_addr undefined; cannot init system counter");
49+
} else {
50+
volatile struct generic_timer_cntctrl* timer_ctl;
51+
timer_ctl = (struct generic_timer_cntctrl*)mem_alloc_map_dev(&cpu()->as,
52+
SEC_HYP_PRIVATE, platform.arch.generic_timer.base_addr,
53+
platform.arch.generic_timer.base_addr, sizeof(struct generic_timer_cntctrl));
54+
55+
timer_ctl->CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN;
56+
fence_ord_write();
57+
58+
timer_freq = (uint32_t)timer_ctl->CNTDIF0;
59+
60+
mem_unmap(&cpu()->as, (vaddr_t)timer_ctl, sizeof(struct generic_timer_cntctrl),
61+
false);
62+
}
63+
#endif
64+
>>>>>>> 0ea60453 (feat(armv8r): handle different timer init cases)
65+
}
66+
}
67+
68+
cpu_sync_barrier(&cpu_glb_sync);
69+
70+
/* Program CNTFRQ_EL0 and verify. */
71+
sysreg_cntfrq_el0_write(timer_freq);
72+
if (sysreg_cntfrq_el0_read() != (unsigned long)timer_freq) {
73+
ERROR("failed to program CNTFRQ_EL0 to %u Hz", timer_freq);
74+
}
75+
}

‎src/arch/armv8/armv8-r/vmm_BASE_2363469.c‎

Lines changed: 38 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
/**
2+
* SPDX-License-Identifier: Apache-2.0
3+
* Copyright (c) Bao Project and Contributors. All rights reserved.
4+
*/
5+
6+
#include <bao.h>
7+
#include <vmm.h>
8+
#include <platform.h>
9+
#include <arch/generic_timer.h>
10+
#include <cpu.h>
11+
#include <fences.h>
12+
13+
static uint32_t timer_freq = 0;
14+
15+
void vmm_arch_profile_init()
16+
{
17+
if (cpu_is_master()) {
18+
/**
19+
* Since there is no firmware in cortex-r platforms, we need to initialize the system
20+
* counter.
21+
*/
22+
volatile struct generic_timer_cntctrl* timer_ctl;
23+
timer_ctl = (struct generic_timer_cntctrl*)mem_alloc_map_dev(&cpu()->as, SEC_HYP_PRIVATE,
24+
platform.arch.generic_timer.base_addr, platform.arch.generic_timer.base_addr,
25+
sizeof(struct generic_timer_cntctrl));
26+
27+
timer_ctl->CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN;
28+
fence_ord_write();
29+
30+
timer_freq = timer_ctl->CNTDIF0;
31+
32+
mem_unmap(&cpu()->as, (vaddr_t)timer_ctl, sizeof(struct generic_timer_cntctrl), false);
33+
}
34+
35+
cpu_sync_barrier(&cpu_glb_sync);
36+
37+
sysreg_cntfrq_el0_write(timer_freq);
38+
}

‎src/arch/armv8/armv8-r/vmm_LOCAL_2363469.c‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,51 @@
1+
/**
2+
* SPDX-License-Identifier: Apache-2.0
3+
* Copyright (c) Bao Project and Contributors. All rights reserved.
4+
*/
5+
6+
#include <bao.h>
7+
#include <vmm.h>
8+
#include <platform.h>
9+
#include <arch/generic_timer.h>
10+
#include <cpu.h>
11+
#include <fences.h>
12+
13+
static uint32_t timer_freq = 0;
14+
15+
void vmm_arch_profile_init()
16+
{
17+
if (cpu_is_master()) {
18+
unsigned long cur_cntfrq = sysreg_cntfrq_el0_read();
19+
if (cur_cntfrq != 0UL) {
20+
timer_freq = (uint32_t)cur_cntfrq;
21+
} else if (platform.arch.generic_timer.fixed_freq != 0)
22+
timer_freq = (uint32_t)PLAT_GENERIC_TIMER_FREQ_HZ;
23+
} else {
24+
25+
if (platform.arch.generic_timer.base_addr == 0) {
26+
ERROR("generic timer base_addr undefined; cannot init system counter");
27+
}
28+
29+
volatile struct generic_timer_cntctrl* timer_ctl;
30+
timer_ctl = (struct generic_timer_cntctrl*)mem_alloc_map_dev(&cpu()->as,
31+
SEC_HYP_PRIVATE, platform.arch.generic_timer.base_addr,
32+
platform.arch.generic_timer.base_addr, sizeof(struct generic_timer_cntctrl));
33+
34+
timer_ctl->CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN;
35+
fence_ord_write();
36+
37+
timer_freq = (uint32_t)timer_ctl->CNTDIF0;
38+
39+
mem_unmap(&cpu()->as, (vaddr_t)timer_ctl, sizeof(struct generic_timer_cntctrl),
40+
false);
41+
}
42+
}
43+
44+
cpu_sync_barrier(&cpu_glb_sync);
45+
46+
/* Program CNTFRQ_EL0 and verify. */
47+
sysreg_cntfrq_el0_write(timer_freq);
48+
if (sysreg_cntfrq_el0_read() != (unsigned long)timer_freq) {
49+
ERROR("failed to program CNTFRQ_EL0 to %u Hz", timer_freq);
50+
}
51+
}

‎src/arch/armv8/armv8-r/vmm_REMOTE_2363469.c‎

Lines changed: 52 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,52 @@
1+
/**
2+
* SPDX-License-Identifier: Apache-2.0
3+
* Copyright (c) Bao Project and Contributors. All rights reserved.
4+
*/
5+
6+
#include <bao.h>
7+
#include <vmm.h>
8+
#include <platform.h>
9+
#include <arch/generic_timer.h>
10+
#include <cpu.h>
11+
#include <fences.h>
12+
13+
static uint32_t timer_freq = 0;
14+
15+
void vmm_arch_profile_init()
16+
{
17+
if (cpu_is_master()) {
18+
unsigned long cur_cntfrq = sysreg_cntfrq_el0_read();
19+
if (cur_cntfrq != 0UL) {
20+
timer_freq = (uint32_t)cur_cntfrq;
21+
} else {
22+
#ifdef PLAT_GENERIC_TIMER_FREQ_HZ
23+
timer_freq = (uint32_t)PLAT_GENERIC_TIMER_FREQ_HZ;
24+
#else
25+
if (platform.arch.generic_timer.base_addr == 0) {
26+
ERROR("generic timer base_addr undefined; cannot init system counter");
27+
} else {
28+
volatile struct generic_timer_cntctrl* timer_ctl;
29+
timer_ctl = (struct generic_timer_cntctrl*)mem_alloc_map_dev(&cpu()->as,
30+
SEC_HYP_PRIVATE, platform.arch.generic_timer.base_addr,
31+
platform.arch.generic_timer.base_addr, sizeof(struct generic_timer_cntctrl));
32+
33+
timer_ctl->CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN;
34+
fence_ord_write();
35+
36+
timer_freq = (uint32_t)timer_ctl->CNTDIF0;
37+
38+
mem_unmap(&cpu()->as, (vaddr_t)timer_ctl, sizeof(struct generic_timer_cntctrl),
39+
false);
40+
}
41+
#endif
42+
}
43+
}
44+
45+
cpu_sync_barrier(&cpu_glb_sync);
46+
47+
/* Program CNTFRQ_EL0 and verify. */
48+
sysreg_cntfrq_el0_write(timer_freq);
49+
if (sysreg_cntfrq_el0_read() != (unsigned long)timer_freq) {
50+
ERROR("failed to program CNTFRQ_EL0 to %u Hz", timer_freq);
51+
}
52+
}

‎src/arch/armv8/inc/arch/platform.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ struct arch_platform {
3232

3333
struct {
3434
paddr_t base_addr;
35+
uint32_t fixed_freq;
3536
} generic_timer;
3637

3738
struct clusters {

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