@@ -15,24 +15,35 @@ static uint32_t timer_freq = 0;
1515void vmm_arch_profile_init ()
1616{
1717 if (cpu_is_master ()) {
18- /**
19- * Since there is no firmware in cortex-r platforms, we need to initialize the system
20- * counter.
21- */
22- volatile struct generic_timer_cntctrl * timer_ctl ;
23- timer_ctl = (struct generic_timer_cntctrl * )mem_alloc_map_dev (& cpu ()-> as , SEC_HYP_PRIVATE ,
24- platform .arch .generic_timer .base_addr , platform .arch .generic_timer .base_addr ,
25- sizeof (struct generic_timer_cntctrl ));
26-
27- timer_ctl -> CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN ;
28- fence_ord_write ();
29-
30- timer_freq = timer_ctl -> CNTDIF0 ;
31-
32- mem_unmap (& cpu ()-> as , (vaddr_t )timer_ctl , sizeof (struct generic_timer_cntctrl ), false);
18+ unsigned long cur_cntfrq = sysreg_cntfrq_el0_read ();
19+ if (cur_cntfrq != 0UL ) {
20+ timer_freq = (uint32_t )cur_cntfrq ;
21+ } else if (platform .arch .generic_timer .fixed_freq != 0 ) {
22+ timer_freq = (uint32_t )platform .arch .generic_timer .fixed_freq ;
23+ } else {
24+ if (platform .arch .generic_timer .base_addr == 0 ) {
25+ ERROR ("generic timer base_addr undefined; cannot init system counter" );
26+ }
27+
28+ volatile struct generic_timer_cntctrl * timer_ctl ;
29+ timer_ctl = (struct generic_timer_cntctrl * )mem_alloc_map_dev (& cpu ()-> as ,
30+ SEC_HYP_PRIVATE , platform .arch .generic_timer .base_addr ,
31+ platform .arch .generic_timer .base_addr , sizeof (struct generic_timer_cntctrl ));
32+
33+ timer_ctl -> CNTCR |= GENERIC_TIMER_CNTCTL_CNTCR_EN ;
34+ fence_ord_write ();
35+
36+ timer_freq = (uint32_t )timer_ctl -> CNTDIF0 ;
37+
38+ mem_unmap (& cpu ()-> as , (vaddr_t )timer_ctl , sizeof (struct generic_timer_cntctrl ), false);
39+ }
3340 }
3441
3542 cpu_sync_barrier (& cpu_glb_sync );
3643
44+ /* Program CNTFRQ_EL0 and verify. */
3745 sysreg_cntfrq_el0_write (timer_freq );
46+ if (sysreg_cntfrq_el0_read () != (unsigned long )timer_freq ) {
47+ ERROR ("failed to program CNTFRQ_EL0 to %u Hz" , timer_freq );
48+ }
3849}
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