diff --git a/rtl/core/sargantana b/rtl/core/sargantana index 338bcc4..95c9867 160000 --- a/rtl/core/sargantana +++ b/rtl/core/sargantana @@ -1 +1 @@ -Subproject commit 338bcc4f9a4007cdccf2f8b58a67c06d1f68c758 +Subproject commit 95c986733407dc0b78f69be0e7b44d856f966498 diff --git a/rtl/drac_openpiton_wrapper.sv b/rtl/drac_openpiton_wrapper.sv index 64a9a44..013eb0e 100644 --- a/rtl/drac_openpiton_wrapper.sv +++ b/rtl/drac_openpiton_wrapper.sv @@ -4,9 +4,8 @@ * Description : Sargantana Wrapper to be used in OpenPiton * History : */ - module drac_openpiton_wrapper - import drac_pkg::*; import hpdcache_pkg::*; import wt_cache_pkg::*; + import drac_pkg::*; import sargantana_icache_pkg::*; import hpdcache_pkg::*; import wt_cache_pkg::*; #( // IO addresses parameter int unsigned NIOSections = 1, @@ -117,7 +116,7 @@ localparam drac_cfg_t DracOpenPitonCfg = '{ // Memory Interface Config MemAddrWidth: 40, - MemDataWidth: 512, + MemDataWidth: DCACHE_BUS_WIDTH, MemIDWidth: 8 }; @@ -140,13 +139,13 @@ logic [39:0] brom_req_address; logic brom_req_valid; // icache wires -logic l1_request_valid; -logic l2_response_valid; -logic [PHY_ADDR_SIZE-1:0] l1_request_paddr; -logic [511:0] l2_response_data; // TODO: LOCALPARAMETERS or PKG definition -logic [1:0] l2_response_seqnum; -logic l2_inval_request; -logic [39:0] l2_inval_addr; +logic l1_request_valid; +logic l2_response_valid; +logic [PHY_ADDR_SIZE-1:0] l1_request_paddr; +logic [ICACHELINE_SIZE-1:0] l2_response_data; +logic [1:0] l2_response_seqnum; +logic l2_inval_request; +logic [39:0] l2_inval_addr; assign l2_response_seqnum = '0; // Miss read interface @@ -348,7 +347,7 @@ cinco_ranch_hpdcache_subsystem_l15_adapter #( .DcacheReadPort (DCACHE_READ_PORT), .DcacheWritePort (DCACHE_WRITE_PORT), .DcacheAmoPort (DCACHE_AMO_PORT), - .IcacheMemDataWidth (512), //L1I cacheline + .IcacheMemDataWidth (ICACHELINE_SIZE), //L1I cacheline .IcacheAddrWidth (40), .HPDcacheMemDataWidth (DracOpenPitonCfg.MemDataWidth), //L1D cacheline .IcacheNoCachableSize (`MSG_DATA_SIZE_8B), // 8B @@ -359,6 +358,7 @@ cinco_ranch_hpdcache_subsystem_l15_adapter #( .hpdcache_mem_resp_w_t (hpdcache_mem_resp_w_t), .hpdcache_mem_id_t (hpdcache_mem_id_t), .hpdcache_mem_addr_t (hpdcache_mem_addr_t), + .hpdcache_nline_t (hpdcache_nline_t), .req_portid_t (req_portid_t) ) l15_adapter_inst( diff --git a/rtl/icache b/rtl/icache index 2b589ee..438e71d 160000 --- a/rtl/icache +++ b/rtl/icache @@ -1 +1 @@ -Subproject commit 2b589ee38756761aa85b6dc63921d0b21e242982 +Subproject commit 438e71d26313e6bfd43fcf86cadab7bc353ab42b diff --git a/rtl/interface_icache/rtl/icache_interface.sv b/rtl/interface_icache/rtl/icache_interface.sv index a23fa6d..c470978 100644 --- a/rtl/interface_icache/rtl/icache_interface.sv +++ b/rtl/interface_icache/rtl/icache_interface.sv @@ -15,6 +15,7 @@ module icache_interface import drac_pkg::*; import riscv_pkg::*; + import sargantana_icache_pkg::*; ( input logic clk_i, input logic rstn_i, @@ -59,8 +60,8 @@ assign do_icache_request_int = req_fetch_icache_i.valid & icache_req_ready_i ; -assign icache_req_bits_vpn_o = req_fetch_icache_i.vaddr[drac_pkg::PHY_VIRT_MAX_ADDR_SIZE-1:12]; -assign icache_req_bits_idx_o = req_fetch_icache_i.vaddr[11:0]; +assign icache_req_bits_vpn_o = req_fetch_icache_i.vaddr[PHY_VIRT_MAX_ADDR_SIZE-1:ICACHE_INDEX_SIZE]; +assign icache_req_bits_idx_o = req_fetch_icache_i.vaddr[ICACHE_INDEX_SIZE-1:0]; assign icache_req_kill_o = req_fetch_icache_i.inval_fetch; // TODO: disabled when is_brom_access?? diff --git a/rtl/interface_icache/rtl/nc_icache_buffer.sv b/rtl/interface_icache/rtl/nc_icache_buffer.sv index 1668921..1679907 100644 --- a/rtl/interface_icache/rtl/nc_icache_buffer.sv +++ b/rtl/interface_icache/rtl/nc_icache_buffer.sv @@ -23,9 +23,9 @@ module nc_icache_buffer import drac_pkg::*, sargantana_icache_pkg::*; #( parameter drac_pkg::drac_cfg_t DRAC_CFG = drac_pkg::DracDefaultConfig, - parameter int unsigned L2_DATA_WIDTH = 512, + parameter int unsigned L2_DATA_WIDTH = ICACHELINE_SIZE, parameter int unsigned L2_NC_DATA_WIDTH = 64, - parameter int unsigned CORE_DATA_WIDTH = 512 + parameter int unsigned CORE_DATA_WIDTH = ICACHELINE_SIZE ) ( input logic clk_i, rstn_i, diff --git a/rtl/openpiton_adapter/rtl/cinco_ranch_hpdcache_subsystem_l15_adapter.sv b/rtl/openpiton_adapter/rtl/cinco_ranch_hpdcache_subsystem_l15_adapter.sv index 47a14fa..95f1d62 100644 --- a/rtl/openpiton_adapter/rtl/cinco_ranch_hpdcache_subsystem_l15_adapter.sv +++ b/rtl/openpiton_adapter/rtl/cinco_ranch_hpdcache_subsystem_l15_adapter.sv @@ -381,7 +381,8 @@ module cinco_ranch_hpdcache_subsystem_l15_adapter .WriteByteMaskEnabled (WriteCoalescingEn), .HPDcacheMemDataWidth (HPDcacheMemDataWidth), .IcacheNoCachableSize (IcacheNoCachableSize), - .IcacheCachableSize (`MSG_DATA_SIZE_64B), // Hardcoded!!! + .IcacheCachableSize ((IcacheMemDataWidth == 512) ? + `MSG_DATA_SIZE_64B : `MSG_DATA_SIZE_32B), .hpdcache_mem_req_t (hpdcache_mem_req_t), .hpdcache_mem_req_w_t (hpdcache_mem_req_w_t), .hpdcache_mem_id_t (hpdcache_mem_id_t), diff --git a/rtl/sargantana_subtile.sv b/rtl/sargantana_subtile.sv index 60e0dc1..db89c51 100644 --- a/rtl/sargantana_subtile.sv +++ b/rtl/sargantana_subtile.sv @@ -1,7 +1,7 @@ `include "hpdcache_typedef.svh" module sargantana_subtile - import drac_pkg::*, sargantana_icache_pkg::*, mmu_pkg::*, hpdcache_pkg::*; + import drac_pkg::*, mmu_pkg::*, hpdcache_pkg::*; #( parameter drac_pkg::drac_cfg_t DracCfg = drac_pkg::DracDefaultConfig, diff --git a/rtl/top_tile.sv b/rtl/top_tile.sv index 00ccd73..3d51bf4 100644 --- a/rtl/top_tile.sv +++ b/rtl/top_tile.sv @@ -78,11 +78,11 @@ module top_tile //------------------------------------------------------------------------------------ //- From L2 - input logic io_mem_grant_valid, - input logic [511:0] io_mem_grant_bits_data, - input logic [1:0] io_mem_grant_bits_addr_beat, - input logic io_mem_grant_inval, - input logic [11:0] io_mem_grant_inval_addr, + input logic io_mem_grant_valid, + input logic [ICACHELINE_SIZE-1:0] io_mem_grant_bits_data, + input logic [1:0] io_mem_grant_bits_addr_beat, + input logic io_mem_grant_inval, + input logic [11:0] io_mem_grant_inval_addr, //---------------------------------------------------------------------------------- @@ -186,11 +186,6 @@ module top_tile ); -// PPN Size is address size - set bits - offset bits -localparam int unsigned ICACHE_NUM_SETS = 64; -localparam int unsigned ICACHE_INDEX_SIZE = $clog2(ICACHE_NUM_SETS) + $clog2(ICACHELINE_SIZE/8); -localparam int unsigned ICACHE_PPN_SIZE = PHY_VIRT_MAX_ADDR_SIZE - ICACHE_INDEX_SIZE; -localparam int unsigned ICACHE_VPN_SIZE = PHY_VIRT_MAX_ADDR_SIZE - ICACHE_INDEX_SIZE; // *** dCache *** parameter HPDCACHE_NREQUESTERS = 2; // Core + PTW @@ -388,7 +383,9 @@ assign debug_reg_rf_rdata_o = debug_reg_out.rf_rdata; // *** iCache *** -nc_icache_buffer nc_icache_bf ( +nc_icache_buffer #( + .DRAC_CFG (DracCfg) +) nc_icache_bf ( .clk_i, .rstn_i, @@ -415,11 +412,12 @@ sargantana_top_icache # ( .KILL_RESP ( 1'b1 ), .LINES_256 ( 1'b0 ), + .ICACHE_SIZE (ICACHE_SIZE), .ICACHE_MEM_BLOCK (ICACHELINE_SIZE/8), // In Bytes + .ASSOCIATIVE (ICACHE_ASSOC), .PADDR_SIZE (PHY_ADDR_SIZE), .ADDR_SIZE (PHY_VIRT_MAX_ADDR_SIZE), - .IDX_BITS_SIZE (12), // TODO: Where does this come from? - .FETCH_WIDHT (ICACHELINE_SIZE) + .FETCH_WIDHT (FETCH_WIDHT) ) icache ( `ifdef INTEL_PHYSICAL_MEM_CTRL .hduspsr_mem_ctrl (hduspsr_mem_ctrl),