inter-core FIFOs get handled in sio-core already

Author: c1570

README.md

@@ -206,7 +206,6 @@ Features:
 - somewhat accurate PIO timings (also, MUCH slower emulation)
 - built-in cycle profiler using markers in the code
 - Dual Core support (by mingpepe)
-- Inter-core FIFO support (incomplete)
 - a WIP demo wiring up several RP2040s using an 8 bit bus and gathering debug info, simulating GPIO latency
   - this is the runner used for developing the [Connomore64](https://github.com/c1570/Connomore64)
 - a lot of dirty hacks and tests not suitable for pushing upstream

src/sio.ts

@@ -26,10 +26,6 @@ const GPIO_HI_OE_XOR = 0x04c; // QSPI output enable XOR
 
 const GPIO_MASK = 0x3fffffff;
 
-const FIFO_ST = 0x050; // Inter-core FIFO status register
-const FIFO_WR = 0x054; // Inter-core FIFO write register
-const FIFO_RD = 0x058; // Inter-core FIFO read register
-
 //SPINLOCK
 const SPINLOCK_ST = 0x5c;
 const SPINLOCK0 = 0x100;
@@ -41,8 +37,6 @@ export class RPSIO {
   qspiGpioValue = 0;
   qspiGpioOutputEnable = 0;
   spinLock = 0;
-  fifoCore0In: number[] = [];
-  fifoCore1In: number[] = [];
   readonly core0;
   readonly core1;
 
@@ -63,20 +57,6 @@ export class RPSIO {
       }
     }
     switch (offset) {
-      case FIFO_RD: {
-        let thisCoreFifo = (core == Core.Core0) ? this.fifoCore0In : this.fifoCore1In;
-        if(thisCoreFifo.length == 0) {
-          // FIXME add IRQ support
-          // console.error("reading from empty FIFO");
-        }
-        return thisCoreFifo.shift() || 0;
-      }
-      case FIFO_ST: {
-        let thisCoreFifo = (core == Core.Core0) ? this.fifoCore0In : this.fifoCore1In;
-        let otherCoreFifo = (core == Core.Core0) ? this.fifoCore1In : this.fifoCore0In;
-        // FIXME add WOF/ROE support
-        return (otherCoreFifo.length < 8 ? 2 : 0) | (thisCoreFifo.length > 0 ? 1 : 0);
-      }
       case GPIO_IN:
         return this.rp2040.gpioValues;
       case GPIO_HI_IN: {
@@ -121,6 +101,7 @@ export class RPSIO {
       case SPINLOCK_ST:
         return this.spinLock;
     }
+    // Divider, Interpolator, FIFO get handled per core in sio-core
     switch (core) {
       case Core.Core0:
         return this.core0.readUint32(offset);
@@ -138,14 +119,6 @@ export class RPSIO {
     const prevGpioValue = this.gpioValue;
     const prevGpioOutputEnable = this.gpioOutputEnable;
     switch (offset) {
-      case FIFO_WR:
-        let otherCoreFifo = (core == Core.Core0) ? this.fifoCore1In : this.fifoCore0In;
-        if(otherCoreFifo.length == 8) {
-          console.error("writing to full FIFO");
-        } else {
-          otherCoreFifo.push(value);
-        }
-        break;
       case GPIO_OUT:
         this.gpioValue = value & GPIO_MASK;
         break;
@@ -195,6 +168,7 @@ export class RPSIO {
         this.qspiGpioOutputEnable ^= value & GPIO_MASK;
         break;
       default:
+        // Divider, Interpolator, FIFO get handled per core in sio-core
         switch (core) {
           case Core.Core0:
             this.core0.writeUint32(offset, value);

src/sio_rp2350.ts

@@ -28,10 +28,6 @@ const GPIO_HI_OE_XOR = 0x04c; // GPIO32..47, QSPI, USB output enable XOR
 
 const GPIO_MASK = 0x3fffffff;
 
-const FIFO_ST = 0x050; // Inter-core FIFO status register
-const FIFO_WR = 0x054; // Inter-core FIFO write register
-const FIFO_RD = 0x058; // Inter-core FIFO read register
-
 //SPINLOCK
 const SPINLOCK_ST = 0x5c;
 const SPINLOCK0 = 0x100;
@@ -43,8 +39,6 @@ export class RPSIO {
   qspiGpioValue = 0;
   qspiGpioOutputEnable = 0;
   spinLock = 0;
-  fifoCore0In: number[] = [];
-  fifoCore1In: number[] = [];
   readonly core0;
   readonly core1;
 
@@ -65,20 +59,6 @@ export class RPSIO {
       }
     }
     switch (offset) {
-      case FIFO_RD: {
-        let thisCoreFifo = (core == Core.Core0) ? this.fifoCore0In : this.fifoCore1In;
-        if(thisCoreFifo.length == 0) {
-          // FIXME add IRQ support
-          // console.error("reading from empty FIFO");
-        }
-        return thisCoreFifo.shift() || 0;
-      }
-      case FIFO_ST: {
-        let thisCoreFifo = (core == Core.Core0) ? this.fifoCore0In : this.fifoCore1In;
-        let otherCoreFifo = (core == Core.Core0) ? this.fifoCore1In : this.fifoCore0In;
-        // FIXME add WOF/ROE support
-        return (otherCoreFifo.length < 8 ? 2 : 0) | (thisCoreFifo.length > 0 ? 1 : 0);
-      }
       case GPIO_IN:
         return this.rp2040.gpioValues;
       case GPIO_HI_IN: {
@@ -123,6 +103,7 @@ export class RPSIO {
       case SPINLOCK_ST:
         return this.spinLock;
     }
+    // Divider, Interpolator, FIFO get handled per core in sio-core
     switch (core) {
       case Core.Core0:
         return this.core0.readUint32(offset);
@@ -140,14 +121,6 @@ export class RPSIO {
     const prevGpioValue = this.gpioValue;
     const prevGpioOutputEnable = this.gpioOutputEnable;
     switch (offset) {
-      case FIFO_WR:
-        let otherCoreFifo = (core == Core.Core0) ? this.fifoCore1In : this.fifoCore0In;
-        if(otherCoreFifo.length == 8) {
-          console.error("writing to full FIFO");
-        } else {
-          otherCoreFifo.push(value);
-        }
-        break;
       case GPIO_OUT:
         this.gpioValue = value & GPIO_MASK;
         break;
@@ -197,6 +170,7 @@ export class RPSIO {
         this.qspiGpioOutputEnable ^= value & GPIO_MASK;
         break;
       default:
+        // Divider, Interpolator, FIFO get handled per core in sio-core
         switch (core) {
           case Core.Core0:
             this.core0.writeUint32(offset, value);