RISC-V RVA23 profile support

[edubart]

Context

The RVA23 profile for RISC-V was ratified, and there are signs of major adoption from both hardware manufacturers and software developers. This includes Canonical's recent announcement requiring RVA23S64 ISA profile starting with Ubuntu 25.10.

To ensure future compatibility, we need to support the full RVA23 profile, which includes many additional extensions beyond what we currently implement.

Relevant documents

The profile and specifications are available in the following PDF documents:

• RISC-V RVA23 profile
• RISC-V unprivileged spec
• RISC-V privileged spec

Mandatory Extensions

To make easy to track what is needed and our progress, here is a table listing all mandatory RVA extensions we should take a look and implement.

Profile	Name	Supported	Description
RVA23U64	I	✅	Base Integer Instruction Set
RVA23U64	M	✅	Integer Multiplication and Division
RVA23U64	A	✅	Atomic Instructions
RVA23U64	F	✅	Single-Precision Floating-Point
RVA23U64	D	✅	Double-Precision Floating-Point
RVA23U64	C	✅	Compressed Instructions
RVA23U64	B	❕	Bit Manipulation
RVA23U64	Zicsr	✅	Control and Status Register Access
RVA23U64	Zicntr	✅	Basic Performance Counters
RVA23U64	Zihpm	✅	Hardware Performance Counters
RVA23U64	Ziccif	☑️	Main memory supports instruction fetch with atomicity requirement
RVA23U64	Ziccrse	☑️	Main memory supports forward progress on LR/SC sequences
RVA23U64	Ziccamoa	☑️	Main memory supports all atomics in A
RVA23U64	Zicclsm	❕	Main memory supports misaligned loads/stores
RVA23U64	Za64rs	☑️	Reservation set size of at most 64 bytes
RVA23U64	Zihintpause	☑️	Pause Hint
RVA23U64	Zic64b	☑️	Cache block size is 64 bytes
RVA23U64	Zicbom		Cache-Block Management
RVA23U64	Zicbop		Cache-Block Prefetching
RVA23U64	Zicboz		Cache-Block Zeroing
RVA23U64	Zfhmin	❕	Half-Precision Floating-Point
RVA23U64	Zkt	☑️	Data-Independent Execution Latency
RVA23U64	V	❗	Vector Computation
RVA23U64	Zvfhmin	❗	Vector minimal half-precision floating-point
RVA23U64	Zvbb	❗	Vector Basic Bit-manipulation
RVA23U64	Zvkt	☑️	Vector Data-Independent Execution Latency
RVA23U64	Zihintntl	☑️	Non-temporal locality hints
RVA23U64	Zicond	❕	Integer conditional operations
RVA23U64	Zimop		May-be-operations
RVA23U64	Zcmop		Compressed may-be-operations
RVA23U64	Zcb	❕	Additional compressed instructions
RVA23U64	Zfa	❕	Additional floating-Point instructions
RVA23U64	Zawrs		Wait-on-reservation-set instructions
RVA23U64	Supm		User-mode pointer masking
RVA23S64	Zifencei	✅	Instruction-Fetch Fence
RVA23S64	Ss1p13		Supervisor Architecture v1.13
RVA23S64	Svbare	✅	Bare mode virtual-memory translation supported
RVA23S64	Sv39	✅	Page-based Virtual Memory, 39-bit
RVA23S64	Svade		Raise exceptions on improper A/D bits
RVA23S64	Ssccptr	☑️	Main memory supports page table reads
RVA23S64	Sstvecd		stvec supports Direct mode
RVA23S64	Sstvala		stval provides all needed values
RVA23S64	Sscounterenw		Support writeable enables for any supported counter
RVA23S64	Svpbmt		Page-Based Memory Types
RVA23S64	Svinval		Fine-Grained Address-Translation Cache Invalidation
RVA23S64	Svnapot		NAPOT Translation Contiguity
RVA23S64	Sstc		Supervisor-mode Timer Interrupts
RVA23S64	Sscofpmf		Count Overflow and Mode-Based Filtering
RVA23S64	Ssnpm		Supervisor-level pointer masking
RVA23S64	Ssu64xl		UXLEN=64 must be supported
RVA23S64	H		Hypervisor
RVA23S64	Ssstateen		State-enable
RVA23S64	Shcounterenw		Support writeable enables for any supported counter
RVA23S64	Shvstvala		vstval provides all needed values
RVA23S64	Shtvala		htval provides all needed values
RVA23S64	Shvstvecd		vstvec supports Direct mode
RVA23S64	Shvsatpa		vsatp supports all modes supported by satp
RVA23S64	Shgatpa		SvNNx4 mode supported for all modes supported by satp, as well as Bare

Note: While some extensions are straightforward to implement, others require significant effort, particularly the Hypervisor (H) and Vector (V) extensions.
Note: Some extensions listed related to the memory model may not need any change, we have to review them.
Note: Extensions which are not too complex and likely to cause a good performance impact in user-space applications are marked with an exclamation mark, and we should consider implementing them first.

Optional Extensions

The following extensions are optional for RVA23 compliance, but some may provide additional value:

Profile	Name	Supported	Category	Description
RVA23U64	Zvkng		Localized	NIST Algorithm Suite with GCM
RVA23U64	Zvksg		Localized	ShangMi Algorithm Suite with GCM
RVA23U64	Zabha		Development	Byte and Halfword Atomic Memory Operations
RVA23U64	Zacas		Development	Atomic Compare-and-Swap (CAS) instructions
RVA23U64	Ziccamoc		Development	Main memory supports atomics in Zacas
RVA23U64	Zvbc		Development	Vector Carryless Multiplication
RVA23U64	Zama16b		Development	Misaligned loads, stores, and AMOs to main memory regions that do not cross anaturally aligned 16-byte boundary are atomic
RVA23U64	Zfh	❕	Expansion	Half-Precision Floating-Point
RVA23U64	Zbc	❕	Expansion	Carryless Multiplication
RVA23U64	Zicfilp		Expansion	Landing Pads
RVA23U64	Zicfiss		Expansion	Shadow Stack
RVA23U64	Zvfh	❗	Expansion	Vector half-precision floating-point
RVA23U64	Zfbfmin		Expansion	Scalar BF16 converts
RVA23U64	Zvfbfmin		Expansion	Vector BF16 converts
RVA23U64	Zvfbfwma		Expansion	Vector BF16 widening mul-add
RVA23S64	Sv48	✅	Expansion	Page-based Virtual Memory, 48-bit
RVA23S64	Sv57	✅	Expansion	Page-based Virtual Memory, 57-bit
RVA23S64	Zkr		Expansion	Entropy Source
RVA23S64	Svadu		Expansion	Hardware Updating of A/D Bits
RVA23S64	Sdtrig		Expansion	Debug triggers
RVA23S64	Ssstrict		Expansion	Unimplemented reserved encodings raise illegal instruction exceptions
RVA23S64	Sspm		Expansion	Supervisor-mode pointer masking

Note: Some optional extensions could provide value with relatively low implementation effort. For example, half-precision floating-point (Zfh/Zvfh) could enable faster inference for small LLMs and other ML workloads.

Subtasks

Some mandatory extensions already have dedicated tracking issues:

• RISC-V Svinval, Svnapot and Svpbmt extensions support #62
• RISC-V Bitmanip and Scalar Cryptographic extensions support #57
• RISC-V Hypervisor extension support #44