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Bug SMA. Wrong Inverter fixed
1 parent 80e223a commit c7a057d

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Lines changed: 3 additions & 2 deletions

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pv/sma/sma.py

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -183,8 +183,9 @@ def GetAllData(self):
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self.pvdata.wr[0].FAC = self.wrmodbus.available_registers[30803].value
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self.pvdata.wr[1].PNow = self.wrmodbus.available_registers[30961].value
186-
self.pvdata.wr[0].UDC = self.wrmodbus.available_registers[30959].value
187-
self.pvdata.wr[0].IDC = self.wrmodbus.available_registers[30957].value
186+
self.pvdata.wr[1].UDC = self.wrmodbus.available_registers[30959].value
187+
self.pvdata.wr[1].IDC = self.wrmodbus.available_registers[30957].value
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self.pvdata.wr[1].FAC = self.wrmodbus.available_registers[30803].value
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self.pvdata.PTotal = self.wrmodbus.available_registers[30775].value
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self.pvdata.Error = "OK" # everything ok, if we reach this line

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