v1.95.1

[cyring]

• [UI] Split tREFI in two cells in Timing_DDR4
• [UI] Raised the ratio range up to the Uncore max ratio
• [CLI][JSON] Renamed tRCD to tRCD_R and tRCD_W added
• [Intel] Allow ODCM on Raptor Lake [RPL]
• [Intel] RPL: voltage of Pcore, Ecore, System Agent
• [Intel] RPL and ADL Chipset device IDs
• [Intel] Decode the RPL IMC and improve DDR5 support
• [Build] Raise MAX_FREQ_HZ up to 7125000000 Hertz
• [Intel] Mobile {Coffee Lake, Kaby Lake} codenames
• [Intel] Braswell codename detection
• [AMD] SYSCFG Configuration Register
• [AMD] Added EPYC 9654
• [AMD] Transparent SME [TSME]
• [AMD] DRAM Data Scrambling [Scrambler]
• [Doc] Misc Skylake IMC timings specified
• [Doc] Removed cpufreq=0 from README.md

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This discussion was created from the release v1.95.1.