hal: renesas: Silicon detection support

Add support for silicon variant detection and preferred values.

Signed-off-by: Ioannis Karachalios <[email protected]>

Author: ioannis-karachalios

smartbond/da1469x_hal/da1469x_pd.c

@@ -17,6 +17,7 @@
  * under the License.
  */
 
+#include <zephyr/arch/common/sys_io.h>
 #include <assert.h>
 #include <stdlib.h>
 #include <stdint.h>
@@ -25,10 +26,9 @@
 #include <da1469x_pd.h>
 #include <da1469x_trimv.h>
 
-/* This shall be defined for each MCU separately */
-extern void da1469x_pd_apply_preferred(uint8_t pd);
+#define PD_COUNT          (sizeof(g_da1469x_pd_desc) / sizeof(g_da1469x_pd_desc[0]))
 
-#define PD_COUNT    (sizeof(g_da1469x_pd_desc) / sizeof(g_da1469x_pd_desc[0]))
+#define REG_TO_PTR(_reg)  ((uintptr_t)&(_reg))
 
 struct da1469x_pd_desc {
     uint8_t pmu_sleep_bit;
@@ -41,6 +41,14 @@ struct da1469x_pd_data {
     uint32_t *trimv_words;
 };
 
+enum chip_variant {
+	CHIP_VARIANT_TSMC,
+	CHIP_VARIANT_GF,
+	CHIP_VARIANT_UNKNOWN
+};
+
+static int g_device_id = CHIP_VARIANT_UNKNOWN;
+
 /* Only include controllable power domains here */
 static const struct da1469x_pd_desc g_da1469x_pd_desc[] = {
     [MCU_PD_DOMAIN_SYS] = { CRG_TOP_PMU_CTRL_REG_SYS_SLEEP_Pos,
@@ -55,6 +63,14 @@ static const struct da1469x_pd_desc g_da1469x_pd_desc[] = {
 
 static struct da1469x_pd_data g_da1469x_pd_data[PD_COUNT];
 
+static inline void
+write32_mask(uint32_t mask, uint32_t data, mem_addr_t addr)
+{
+	uint32_t val = sys_read32(addr);
+
+	sys_write32((val & (~mask)) | (data & mask), addr);
+}
+
 static void
 da1469x_pd_load_trimv(uint8_t pd, uint8_t group)
 {
@@ -102,9 +118,104 @@ da1469x_pd_apply_trimv(uint8_t pd)
     }
 }
 
+static int
+read_device_id(void)
+{
+	union {
+		uint8_t array[4];
+		uint32_t value;
+	} chip_id;
+
+	chip_id.array[3] = CHIP_VERSION->CHIP_ID1_REG & CHIP_VERSION_CHIP_ID1_REG_CHIP_ID1_Msk;
+	chip_id.array[2] = CHIP_VERSION->CHIP_ID2_REG & CHIP_VERSION_CHIP_ID2_REG_CHIP_ID2_Msk;
+	chip_id.array[1] = CHIP_VERSION->CHIP_ID3_REG & CHIP_VERSION_CHIP_ID3_REG_CHIP_ID3_Msk;
+	chip_id.array[0] = CHIP_VERSION->CHIP_ID4_REG & CHIP_VERSION_CHIP_ID4_REG_CHIP_ID4_Msk;
+
+	if (chip_id.value == 0x32353232) {
+		return CHIP_VARIANT_TSMC;
+	} else if (chip_id.value == 0x33303830) {
+		return CHIP_VARIANT_GF;
+	} else {
+		return CHIP_VARIANT_UNKNOWN;
+	}
+}
+
+static void 
+da1469x_TSMC_pd_apply_preferred(uint8_t pd)
+{
+	switch (pd) {
+	case MCU_PD_DOMAIN_AON:
+	    /* Apply if no user-defined value has been applied */
+		if (sys_read32(REG_TO_PTR(CRG_TOP->PMU_TRIM_REG)) == 0x00008800) {
+			sys_write32(0x00007700, REG_TO_PTR(CRG_TOP->PMU_TRIM_REG));
+		}
+		write32_mask(0x00001000, 0x00001020, REG_TO_PTR(CRG_TOP->BANDGAP_REG));
+		sys_write32(0x000000ca, REG_TO_PTR(CRG_TOP->BIAS_VREF_SEL_REG));
+		write32_mask(0x0003ffff, 0x041e6ef4, REG_TO_PTR(CRG_TOP->BOD_LVL_CTRL0_REG));
+		break;
+	case MCU_PD_DOMAIN_SYS:
+		write32_mask(0x00000c00, 0x003f6a78, REG_TO_PTR(CHARGER->CHARGER_CTRL_REG));
+		write32_mask(0x000003ff, 0x00000002, REG_TO_PTR(CHARGER->CHARGER_PWR_UP_TIMER_REG));
+		break;
+	case MCU_PD_DOMAIN_TIM:
+		write32_mask(0x3ff00000, 0x000afd70, REG_TO_PTR(CRG_XTAL->CLK_FREQ_TRIM_REG));
+		write32_mask(0x000000c0, 0x00000562, REG_TO_PTR(CRG_XTAL->TRIM_CTRL_REG));
+		write32_mask(0x03c38002, 0x0801e6b6, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL0_REG)); 
+		write32_mask(0x007fff00, 0x7500a1a4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL1_REG));
+		write32_mask(0x00000fff, 0x001e45c4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL2_REG));
+		write32_mask(0x40000000, 0x40096255, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL3_REG));
+		write32_mask(0x00c00000, 0x00c00000, 0x50010040);
+		write32_mask(0x000000ff, 0x00000180, REG_TO_PTR(CRG_XTAL->XTALRDY_CTRL_REG));
+		break;
+	}
+}
+
+static void 
+da1469x_GF_pd_apply_preferred(uint8_t pd)
+{
+	switch (pd) {
+	case MCU_PD_DOMAIN_AON:
+		write32_mask(0x00001000, 0x00001020, REG_TO_PTR(CRG_TOP->BANDGAP_REG));
+		sys_write32(0x000000ca, REG_TO_PTR(CRG_TOP->BIAS_VREF_SEL_REG));
+		write32_mask(0x0003ffff, 0x041e6ef4, REG_TO_PTR(CRG_TOP->BOD_LVL_CTRL0_REG));
+		write32_mask(0x00000f00, 0x00000dfc, REG_TO_PTR(CRG_TOP->CLK_RCX_REG));
+		write32_mask(0x0000007e, 0x00000024, REG_TO_PTR(CRG_TOP->CLK_XTAL32K_REG));
+		break;
+	case MCU_PD_DOMAIN_SYS:
+		write32_mask(0x00000c00, 0x003f6a78, REG_TO_PTR(CHARGER->CHARGER_CTRL_REG));
+		write32_mask(0x000003ff, 0x00000002, REG_TO_PTR(CHARGER->CHARGER_PWR_UP_TIMER_REG));
+		break;
+	case MCU_PD_DOMAIN_TIM:
+		write32_mask(0x3ff00000, 0x000afd70, REG_TO_PTR(CRG_XTAL->CLK_FREQ_TRIM_REG));
+		write32_mask(0x000000c0, 0x00000562, REG_TO_PTR(CRG_XTAL->TRIM_CTRL_REG));
+		write32_mask(0x1fc38002, 0x0c01e6b6, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL0_REG)); 
+		write32_mask(0x707fff00, 0x0500a1a4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL1_REG));
+		write32_mask(0x00000fff, 0x001e45c4, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL2_REG));
+		write32_mask(0x40000000, 0x40096255, REG_TO_PTR(CRG_XTAL->XTAL32M_CTRL3_REG));
+		write32_mask(0x00c00000, 0x00c00000, 0x50010040);
+		write32_mask(0x000000ff, 0x00000180, REG_TO_PTR(CRG_XTAL->XTALRDY_CTRL_REG));
+		break;
+	}
+}
+
+__weak void
+da1469x_pd_apply_preferred(uint8_t pd)
+{
+	if (g_device_id == CHIP_VARIANT_TSMC) {
+		da1469x_TSMC_pd_apply_preferred(pd);
+	} else {
+		da1469x_GF_pd_apply_preferred(pd);
+	}
+}
+
+
 int
 da1469x_pd_init(void)
 {
+    /* Get the chip ID before initilizating any PD */
+	g_device_id = read_device_id();
+	assert(g_device_id != CHIP_VARIANT_UNKNOWN);
+
     /*
      * Apply now for always-on domain which, as name suggests, is always on so
      * need to do this only once.