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Merge pull request #869 from diffblue/verilog-retain-explicit-casts
SystemVerilog: retain explicit casts
2 parents 4b62b9e + 1c7f0ae commit 798b5e0

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15 files changed

+218
-31
lines changed

15 files changed

+218
-31
lines changed

regression/verilog/case/riscv-alu.desc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -4,11 +4,11 @@ riscv-alu.sv
44
^\[alu\.pADD\] always alu\.op == \{ 7'b0000000, 3'b000 \} -> alu\.out == alu\.a \+ alu\.b: PROVED up to bound 0$
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^\[alu\.pSUB\] always alu\.op == \{ 7'b0100000, 3'b000 \} -> alu\.out == alu\.a - alu\.b: PROVED up to bound 0$
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^\[alu\.pSLL\] always alu\.op == \{ 7'b0000000, 3'b001 \} -> alu\.out == alu\.a << alu\.b\[4:0\]: PROVED up to bound 0$
7-
^\[alu\.pSLT\] always alu\.op == \{ 7'b0000000, 3'b010 \} -> alu\.out == alu\.a < alu\.b: PROVED up to bound 0$
7+
^\[alu\.pSLT\] always alu\.op == \{ 7'b0000000, 3'b010 \} -> alu\.out == \$signed\(alu\.a\) < \$signed\(alu\.b\): PROVED up to bound 0$
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^\[alu\.pSLTU\] always alu\.op == \{ 7'b0000000, 3'b011 \} -> alu\.out == alu\.a < alu\.b: PROVED up to bound 0$
99
^\[alu\.pXOR\] always alu\.op == \{ 7'b0000000, 3'b100 \} -> alu\.out == \(alu\.a \^ alu\.b\): PROVED up to bound 0$
1010
^\[alu\.pSRL\] always alu\.op == \{ 7'b0000000, 3'b101 \} -> alu\.out == alu\.a >> alu\.b\[4:0\]: PROVED up to bound 0$
11-
^\[alu\.pSRA\] always alu\.op == \{ 7'b0100000, 3'b101 \} -> alu\.out == alu\.a >>> alu\.b\[4:0\]: PROVED up to bound 0$
11+
^\[alu\.pSRA\] always alu\.op == \{ 7'b0100000, 3'b101 \} -> alu\.out == \$signed\(alu\.a\) >>> alu\.b\[4:0\]: PROVED up to bound 0$
1212
^\[alu\.pOR\] always alu\.op == \{ 7'b0000000, 3'b110 \} -> alu\.out == \(alu\.a | alu\.b\): PROVED up to bound 0$
1313
^\[alu\.pAND\] always alu\.op == \{ 7'b0000000, 3'b111 \} -> alu\.out == \(alu\.a & alu\.b\): PROVED up to bound 0$
1414
^EXIT=0$

regression/verilog/enums/enum4.desc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,5 +3,5 @@ enum4.sv
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--bound 0
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^EXIT=0$
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^SIGNAL=0$
6-
^\[main\.p1\] always main\.A == 1: PROVED up to bound 0$
6+
^\[main\.p1\] always main\.A == \[7:0\]'\(1\): PROVED up to bound 0$
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--

regression/verilog/enums/enum_cast1.desc

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,6 @@ enum_cast1.sv
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--bound 0
44
^EXIT=0$
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^SIGNAL=0$
6-
^\[main\.p1\] always main.A == 1: PROVED up to bound 0$
7-
^\[main\.p2\] always main.B == 2: PROVED up to bound 0$
6+
^\[main\.p1\] always main.A == signed \[31:0\]'\(1\): PROVED up to bound 0$
7+
^\[main\.p2\] always main.B == signed \[31:0\]'\(2\): PROVED up to bound 0$
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--

regression/verilog/expressions/signed1.desc

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Original file line numberDiff line numberDiff line change
@@ -1,6 +1,14 @@
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CORE
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signed1.sv
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--module main --bound 0
4+
^\[main\.p1\] always main\.wire1 == main.wire2: PROVED up to bound 0$
5+
^\[main\.p2\] always main\.wire1 >>> 1 == -1: PROVED up to bound 0$
6+
^\[main\.p3\] always main\.wire2 >> 1 != -1: PROVED up to bound 0$
7+
^\[main\.p4\] always main\.wire1\[31:0\] >> 1 != -1: PROVED up to bound 0$
8+
^\[main\.p5\] always \$unsigned\(main\.wire1\) >> 1 != -1: PROVED up to bound 0$
9+
^\[main\.p6\] always \$signed\(main\.wire2\) >>> 1 == -1: PROVED up to bound 0$
10+
^\[main\.p7\] always -1 >> 1 != -1: PROVED up to bound 0$
11+
^\[main\.p8\] always -1 >>> 1 == -1: PROVED up to bound 0$
412
^EXIT=0$
513
^SIGNAL=0$
614
--

regression/verilog/expressions/size_cast1.desc

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@@ -1,6 +1,10 @@
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CORE
22
size_cast1.sv
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--module main --bound 0
4+
^\[main\.p0\] always \$bits\(10'\(1\)\) == 10: PROVED up to bound 0$
5+
^\[main\.p1\] always \$bits\(20'\(1\)\) == 20: PROVED up to bound 0$
6+
^\[main\.p2\] always 10'\(-1\) == -1: PROVED up to bound 0$
7+
^\[main\.p3\] always 2'\(1 == 1\) == 1: PROVED up to bound 0$
48
^EXIT=0$
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^SIGNAL=0$
610
--

regression/verilog/expressions/size_cast1.sv

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@@ -7,4 +7,7 @@ module main;
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p2: assert final (10'(-1) == -1);
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p3: assert final (2'(1==1) == 1);
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10+
// size-casts yield constants
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parameter Q = 10'(1);
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1013
endmodule
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@@ -1,8 +1,8 @@
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CORE
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static_cast1.sv
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--module main --bound 0
4+
^\[main\.p0\] always \[7:0\]'\(32'hFFFF\) == 255: PROVED up to bound 0$
45
^EXIT=0$
56
^SIGNAL=0$
6-
^\[main\.p0\] always 32'hFFFF == 255: PROVED up to bound 0$
77
--
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^warning: ignoring

regression/verilog/expressions/static_cast1.sv

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Original file line numberDiff line numberDiff line change
@@ -4,4 +4,7 @@ module main;
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p0: assert final (eight_bits'('hffff) == 'hff);
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7+
// static casts yield constants
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parameter Q = eight_bits'('hffff);
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710
endmodule
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@@ -0,0 +1,7 @@
1+
CORE
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signed1.v
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--bound 0
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^EXIT=10$
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^SIGNAL=0$
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--
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^warning: ignoring
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@@ -0,0 +1,5 @@
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module main;
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parameter Q = $signed(123);
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endmodule

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