CI

Model baud rate generator and SCLK divider #18523

Sign in to view logs

Triggered via pull request March 14, 2026 06:25

bugadani

synchronize #5186

bugadani:uart-sclk-rework

Status Success

Total duration 15m 45s

Artifacts –

ci.yml

on: pull_request

get-labels / get-labels

Matrix: build-tests-full

detect-extras-runner / detect-runner

detect-host-tests-runner / detect-runner

Matrix: docs

Matrix: esp-hal

Matrix: msrv

Annotations

1 notice

Summary report available at: https://github.com/esp-rs/esp-hal/actions/runs/23082302300#summary-67053571449