Moved sleep timer wake-up into the existing UlpCoreWakeupSource enum, which allows ULP Timer to be disabled, and preserves backwards-compatibility

Author: leighleighleigh

esp-hal/src/soc/esp32s2/ulp_core.rs

@@ -48,22 +48,25 @@ use crate::peripherals::LPWR;
 pub enum UlpCoreWakeupSource {
     /// Wakeup source from the HP (High Performance) CPU.
     HpCpu,
+    /// Wakeup after the ULP Timer has elapsed.
+    /// The actual period between wake-ups is affected by the runtime duration of the ULP program.
+    Timer(UlpCoreTimerCycles),
 }
 
-/// Configures `RTC_CNTL_ULP_CP_TIMER_1_REG` to set sleep cycles for ULP coprocessor timer.
+/// ULP Timer cycles are clocked at a rate of approximately 8MHz / 32768  = ~244 Hz.
 #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
-pub struct UlpCoreSleepCycles {
+pub struct UlpCoreTimerCycles {
     cycles: u32,
 }
-impl UlpCoreSleepCycles {
-    /// Creates a new sleep cycle configuration.
+impl UlpCoreTimerCycles {
+    /// Creates a new Ulp Timer cycle count configuration.
     /// ## Panics
     ///
     /// Panics if the cycles value is outside of the value range (0 ..= 0xFFFFFF).
     pub const fn new(cycles: u32) -> Self {
         ::core::assert!(
             cycles <= 0xFFFFFF,
-            "`RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE` sleep cycles must be between 0 and 0xFFFFFF (inclusive)."
+            "ULP Timer cycles must be between 0 and 0xFFFFFF (inclusive)."
         );
         Self { cycles }
     }
@@ -74,7 +77,7 @@ impl UlpCoreSleepCycles {
         self.cycles()
     }
 }
-impl Default for UlpCoreSleepCycles {
+impl Default for UlpCoreTimerCycles {
     fn default() -> Self {
         // ESP32-S2 Technical Reference Manual. Register 1.2. RTC_CNTL_ULP_CP_TIMER_1_REG (0x0130)
         // Field RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE has a default value of 200 cycles.
@@ -102,15 +105,6 @@ impl<'d> UlpCore<'d> {
         }
     }
 
-    /// Sets the number of ULP Timer cycles to wait after the ULP halts, before starting it again.
-    /// ULP Timer cycles are clocked at a rate of approximately 8MHz / 32768  = ~244 Hz.
-    /// The actual period between wake-ups is affected by the runtime duration of the ULP program.
-    pub fn with_sleep_cycles(self, cycles: UlpCoreSleepCycles) -> Self {
-        let mut x = self;
-        x._sleep_cycles = cycles;
-        x
-    }
-
     // currently stopping the ULP doesn't work (while following the procedures
     // outlined in the TRM) - so don't offer this function for now
     //
@@ -125,13 +119,6 @@ impl<'d> UlpCore<'d> {
     }
 }
 
-fn ulp_set_wakeup_period(sleep_cycles: UlpCoreSleepCycles) {
-    let cycles = sleep_cycles.value() << 8;
-    LPWR::regs()
-        .ulp_cp_timer_1()
-        .write(|w| unsafe { w.ulp_cp_timer_slp_cycle().bits(cycles) });
-}
-
 #[allow(unused)] // TODO: remove cfg when implementation is corrected
 fn ulp_stop() {
     LPWR::regs()
@@ -193,7 +180,15 @@ fn ulp_run(wakeup_src: UlpCoreWakeupSource) {
 fn ulp_config_wakeup_source(wakeup_src: UlpCoreWakeupSource) {
     match wakeup_src {
         UlpCoreWakeupSource::HpCpu => {
-            // use timer to wake up
+            // only wake-up when the HpCpu calls .run()
+        },
+        UlpCoreWakeupSource::Timer(sleep_cycles) => {
+            // configure timer duration
+            let cycles = sleep_cycles.value() << 8;
+            LPWR::regs()
+                .ulp_cp_timer_1()
+                .write(|w| unsafe { w.ulp_cp_timer_slp_cycle().bits(cycles) });
+            // enable the timer
             LPWR::regs()
                 .ulp_cp_ctrl()
                 .modify(|_, w| w.ulp_cp_force_start_top().clear_bit());

esp-hal/src/soc/esp32s3/ulp_core.rs

@@ -48,22 +48,25 @@ use crate::peripherals::LPWR;
 pub enum UlpCoreWakeupSource {
     /// Wakeup source from the HP (High Performance) CPU.
     HpCpu,
+    /// Wakeup after the ULP Timer has elapsed.
+    /// The actual period between wake-ups is affected by the runtime duration of the ULP program.
+    Timer(UlpCoreTimerCycles),
 }
 
-/// Configures `RTC_CNTL_ULP_CP_TIMER_1_REG` to set sleep cycles for ULP coprocessor timer.
+/// ULP Timer cycles are clocked at a rate of approximately 17.5MHz / 32768  = ~534 Hz.
 #[derive(Debug, Clone, Copy, PartialEq, Eq, Hash)]
-pub struct UlpCoreSleepCycles {
+pub struct UlpCoreTimerCycles {
     cycles: u32,
 }
-impl UlpCoreSleepCycles {
-    /// Creates a new sleep cycle configuration.
+impl UlpCoreTimerCycles {
+    /// Creates a new Ulp Timer cycle count configuration.
     /// ## Panics
     ///
     /// Panics if the cycles value is outside of the value range (0 ..= 0xFFFFFF).
     pub const fn new(cycles: u32) -> Self {
         ::core::assert!(
             cycles <= 0xFFFFFF,
-            "`RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE` sleep cycles must be between 0 and 0xFFFFFF (inclusive)."
+            "ULP Timer cycles must be between 0 and 0xFFFFFF (inclusive)."
         );
         Self { cycles }
     }
@@ -74,7 +77,7 @@ impl UlpCoreSleepCycles {
         self.cycles()
     }
 }
-impl Default for UlpCoreSleepCycles {
+impl Default for UlpCoreTimerCycles {
     fn default() -> Self {
         // ESP32-S3 Technical Reference Manual. Register 2.2. RTC_CNTL_ULP_CP_TIMER_1_REG (0x0134)
         // Field RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE has a default value of 200 cycles.
@@ -85,15 +88,13 @@ impl Default for UlpCoreSleepCycles {
 /// Structure representing the ULP (Ultra-Low Power) core.
 pub struct UlpCore<'d> {
     _lp_core: crate::peripherals::ULP_RISCV_CORE<'d>,
-    _sleep_cycles: UlpCoreSleepCycles,
 }
 
 impl<'d> UlpCore<'d> {
     /// Creates a new instance of the `UlpCore` struct.
     pub fn new(lp_core: crate::peripherals::ULP_RISCV_CORE<'d>) -> Self {
         let mut this = Self {
             _lp_core: lp_core,
-            _sleep_cycles: Default::default(),
         };
         this.stop();
 
@@ -105,34 +106,17 @@ impl<'d> UlpCore<'d> {
         this
     }
 
-    /// Sets the number of ULP Timer cycles to wait after the ULP halts, before starting it again.
-    /// ULP Timer cycles are clocked at a rate of approximately 17.5MHz / 32768  = ~534 Hz.
-    /// The actual period between wake-ups is affected by the runtime duration of the ULP program.
-    pub fn with_sleep_cycles(self, cycles: UlpCoreSleepCycles) -> Self {
-        let mut x = self;
-        x._sleep_cycles = cycles;
-        x
-    }
-
     /// Stops the ULP core.
     pub fn stop(&mut self) {
         ulp_stop();
     }
 
     /// Runs the ULP core with the specified wakeup source.
     pub fn run(&mut self, wakeup_src: UlpCoreWakeupSource) {
-        ulp_set_wakeup_period(self._sleep_cycles);
         ulp_run(wakeup_src);
     }
 }
 
-fn ulp_set_wakeup_period(sleep_cycles: UlpCoreSleepCycles) {
-    let cycles = sleep_cycles.value() << 8;
-    LPWR::regs()
-        .ulp_cp_timer_1()
-        .write(|w| unsafe { w.ulp_cp_timer_slp_cycle().bits(cycles) });
-}
-
 fn ulp_stop() {
     let rtc_cntl = LPWR::regs();
     rtc_cntl
@@ -222,15 +206,24 @@ fn ulp_run(wakeup_src: UlpCoreWakeupSource) {
 }
 
 fn ulp_config_wakeup_source(wakeup_src: UlpCoreWakeupSource) {
+    // ESP-IDF source: https://github.com/espressif/esp-idf/blob/12f36a021f511cd4de41d3fffff146c5336ac1e7/components/ulp/ulp_riscv/ulp_riscv.c#L87
     match wakeup_src {
         UlpCoreWakeupSource::HpCpu => {
-            // use timer to wake up
+            // only wake-up when the HpCpu calls .run()
+        },
+        UlpCoreWakeupSource::Timer(sleep_cycles) => {
+            // configure timer duration
+            let cycles = sleep_cycles.value() << 8;
+            LPWR::regs()
+                .ulp_cp_timer_1()
+                .write(|w| unsafe { w.ulp_cp_timer_slp_cycle().bits(cycles) });
+            // enable the timer
             LPWR::regs()
                 .ulp_cp_ctrl()
                 .modify(|_, w| w.ulp_cp_force_start_top().clear_bit());
             LPWR::regs()
                 .ulp_cp_timer()
                 .modify(|_, w| w.ulp_cp_slp_timer_en().set_bit());
-        }
+        },
     }
-}
+}