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tom-vanerhankur
tom-van
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erhankur
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flash/nor/nrf5: drop nrf5 info command
The command substantially complicates support of nRF53/91 series. It was not even properly ported to nRF52. The informative value is disputable. Who wants to see e.g. override trim values for radio or unique device ID? Drop it and simplify the driver. Change-Id: Ia7fb20ce2ebf16065705c5d18deaf934e58db426 Signed-off-by: Tomas Vanek <[email protected]> Reviewed-on: https://review.openocd.org/c/openocd/+/8108 Tested-by: jenkins Reviewed-by: Antonio Borneo <[email protected]>
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‎doc/openocd.texi

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Original file line numberDiff line numberDiff line change
@@ -7319,10 +7319,6 @@ works only for chips that do not have factory pre-programmed region 0
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code.
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@end deffn
73217321

7322-
@deffn {Command} {nrf5 info}
7323-
Decodes and shows information from FICR and UICR registers.
7324-
@end deffn
7325-
73267322
@end deffn
73277323

73287324
@deffn {Flash Driver} {ocl}

‎src/flash/nor/nrf5.c

Lines changed: 0 additions & 166 deletions
Original file line numberDiff line numberDiff line change
@@ -46,32 +46,6 @@ enum nrf5_ficr_registers {
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* On nRF52 is present but not documented */
4747
NRF5_FICR_CONFIGID = NRF5_FICR_REG(0x05C),
4848

49-
NRF5_FICR_DEVICEID0 = NRF5_FICR_REG(0x060),
50-
NRF5_FICR_DEVICEID1 = NRF5_FICR_REG(0x064),
51-
NRF5_FICR_ER0 = NRF5_FICR_REG(0x080),
52-
NRF5_FICR_ER1 = NRF5_FICR_REG(0x084),
53-
NRF5_FICR_ER2 = NRF5_FICR_REG(0x088),
54-
NRF5_FICR_ER3 = NRF5_FICR_REG(0x08C),
55-
NRF5_FICR_IR0 = NRF5_FICR_REG(0x090),
56-
NRF5_FICR_IR1 = NRF5_FICR_REG(0x094),
57-
NRF5_FICR_IR2 = NRF5_FICR_REG(0x098),
58-
NRF5_FICR_IR3 = NRF5_FICR_REG(0x09C),
59-
NRF5_FICR_DEVICEADDRTYPE = NRF5_FICR_REG(0x0A0),
60-
NRF5_FICR_DEVICEADDR0 = NRF5_FICR_REG(0x0A4),
61-
NRF5_FICR_DEVICEADDR1 = NRF5_FICR_REG(0x0A8),
62-
63-
NRF51_FICR_OVERRIDEN = NRF5_FICR_REG(0x0AC),
64-
NRF51_FICR_NRF_1MBIT0 = NRF5_FICR_REG(0x0B0),
65-
NRF51_FICR_NRF_1MBIT1 = NRF5_FICR_REG(0x0B4),
66-
NRF51_FICR_NRF_1MBIT2 = NRF5_FICR_REG(0x0B8),
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NRF51_FICR_NRF_1MBIT3 = NRF5_FICR_REG(0x0BC),
68-
NRF51_FICR_NRF_1MBIT4 = NRF5_FICR_REG(0x0C0),
69-
NRF51_FICR_BLE_1MBIT0 = NRF5_FICR_REG(0x0EC),
70-
NRF51_FICR_BLE_1MBIT1 = NRF5_FICR_REG(0x0F0),
71-
NRF51_FICR_BLE_1MBIT2 = NRF5_FICR_REG(0x0F4),
72-
NRF51_FICR_BLE_1MBIT3 = NRF5_FICR_REG(0x0F8),
73-
NRF51_FICR_BLE_1MBIT4 = NRF5_FICR_REG(0x0FC),
74-
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/* Following registers are available on nRF52 and on nRF51 since rev 3 */
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NRF5_FICR_INFO_PART = NRF5_FICR_REG(0x100),
7751
NRF5_FICR_INFO_VARIANT = NRF5_FICR_REG(0x104),
@@ -87,9 +61,6 @@ enum nrf5_uicr_registers {
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#define NRF5_UICR_REG(offset) (NRF5_UICR_BASE + offset)
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8963
NRF51_UICR_CLENR0 = NRF5_UICR_REG(0x000),
90-
NRF51_UICR_RBPCONF = NRF5_UICR_REG(0x004),
91-
NRF51_UICR_XTALFREQ = NRF5_UICR_REG(0x008),
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NRF51_UICR_FWID = NRF5_UICR_REG(0x010),
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};
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9566
enum nrf5_nvmc_registers {
@@ -1251,136 +1222,6 @@ COMMAND_HANDLER(nrf5_handle_mass_erase_command)
12511222
return res;
12521223
}
12531224

1254-
COMMAND_HANDLER(nrf5_handle_info_command)
1255-
{
1256-
int res;
1257-
struct flash_bank *bank = NULL;
1258-
struct target *target = get_current_target(CMD_CTX);
1259-
1260-
res = get_flash_bank_by_addr(target, NRF5_FLASH_BASE, true, &bank);
1261-
if (res != ERROR_OK)
1262-
return res;
1263-
1264-
assert(bank);
1265-
1266-
struct nrf5_bank *nbank = bank->driver_priv;
1267-
assert(nbank);
1268-
struct nrf5_info *chip = nbank->chip;
1269-
assert(chip);
1270-
1271-
static struct {
1272-
const uint32_t address;
1273-
uint32_t value;
1274-
} ficr[] = {
1275-
{ .address = NRF5_FICR_CODEPAGESIZE },
1276-
{ .address = NRF5_FICR_CODESIZE },
1277-
{ .address = NRF51_FICR_CLENR0 },
1278-
{ .address = NRF51_FICR_PPFC },
1279-
{ .address = NRF51_FICR_NUMRAMBLOCK },
1280-
{ .address = NRF51_FICR_SIZERAMBLOCK0 },
1281-
{ .address = NRF51_FICR_SIZERAMBLOCK1 },
1282-
{ .address = NRF51_FICR_SIZERAMBLOCK2 },
1283-
{ .address = NRF51_FICR_SIZERAMBLOCK3 },
1284-
{ .address = NRF5_FICR_CONFIGID },
1285-
{ .address = NRF5_FICR_DEVICEID0 },
1286-
{ .address = NRF5_FICR_DEVICEID1 },
1287-
{ .address = NRF5_FICR_ER0 },
1288-
{ .address = NRF5_FICR_ER1 },
1289-
{ .address = NRF5_FICR_ER2 },
1290-
{ .address = NRF5_FICR_ER3 },
1291-
{ .address = NRF5_FICR_IR0 },
1292-
{ .address = NRF5_FICR_IR1 },
1293-
{ .address = NRF5_FICR_IR2 },
1294-
{ .address = NRF5_FICR_IR3 },
1295-
{ .address = NRF5_FICR_DEVICEADDRTYPE },
1296-
{ .address = NRF5_FICR_DEVICEADDR0 },
1297-
{ .address = NRF5_FICR_DEVICEADDR1 },
1298-
{ .address = NRF51_FICR_OVERRIDEN },
1299-
{ .address = NRF51_FICR_NRF_1MBIT0 },
1300-
{ .address = NRF51_FICR_NRF_1MBIT1 },
1301-
{ .address = NRF51_FICR_NRF_1MBIT2 },
1302-
{ .address = NRF51_FICR_NRF_1MBIT3 },
1303-
{ .address = NRF51_FICR_NRF_1MBIT4 },
1304-
{ .address = NRF51_FICR_BLE_1MBIT0 },
1305-
{ .address = NRF51_FICR_BLE_1MBIT1 },
1306-
{ .address = NRF51_FICR_BLE_1MBIT2 },
1307-
{ .address = NRF51_FICR_BLE_1MBIT3 },
1308-
{ .address = NRF51_FICR_BLE_1MBIT4 },
1309-
}, uicr[] = {
1310-
{ .address = NRF51_UICR_CLENR0, },
1311-
{ .address = NRF51_UICR_RBPCONF },
1312-
{ .address = NRF51_UICR_XTALFREQ },
1313-
{ .address = NRF51_UICR_FWID },
1314-
};
1315-
1316-
for (size_t i = 0; i < ARRAY_SIZE(ficr); i++) {
1317-
res = target_read_u32(chip->target, ficr[i].address,
1318-
&ficr[i].value);
1319-
if (res != ERROR_OK) {
1320-
LOG_ERROR("Couldn't read %" PRIx32, ficr[i].address);
1321-
return res;
1322-
}
1323-
}
1324-
1325-
for (size_t i = 0; i < ARRAY_SIZE(uicr); i++) {
1326-
res = target_read_u32(chip->target, uicr[i].address,
1327-
&uicr[i].value);
1328-
if (res != ERROR_OK) {
1329-
LOG_ERROR("Couldn't read %" PRIx32, uicr[i].address);
1330-
return res;
1331-
}
1332-
}
1333-
1334-
command_print(CMD,
1335-
"\n[factory information control block]\n\n"
1336-
"code page size: %"PRIu32"B\n"
1337-
"code memory size: %"PRIu32"kB\n"
1338-
"code region 0 size: %"PRIu32"kB\n"
1339-
"pre-programmed code: %s\n"
1340-
"number of ram blocks: %"PRIu32"\n"
1341-
"ram block 0 size: %"PRIu32"B\n"
1342-
"ram block 1 size: %"PRIu32"B\n"
1343-
"ram block 2 size: %"PRIu32"B\n"
1344-
"ram block 3 size: %"PRIu32 "B\n"
1345-
"config id: %" PRIx32 "\n"
1346-
"device id: 0x%"PRIx32"%08"PRIx32"\n"
1347-
"encryption root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1348-
"identity root: 0x%08"PRIx32"%08"PRIx32"%08"PRIx32"%08"PRIx32"\n"
1349-
"device address type: 0x%"PRIx32"\n"
1350-
"device address: 0x%"PRIx32"%08"PRIx32"\n"
1351-
"override enable: %"PRIx32"\n"
1352-
"NRF_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1353-
"BLE_1MBIT values: %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32" %"PRIx32"\n"
1354-
"\n[user information control block]\n\n"
1355-
"code region 0 size: %"PRIu32"kB\n"
1356-
"read back protection configuration: %"PRIx32"\n"
1357-
"reset value for XTALFREQ: %"PRIx32"\n"
1358-
"firmware id: 0x%04"PRIx32,
1359-
ficr[0].value,
1360-
(ficr[1].value * ficr[0].value) / 1024,
1361-
(ficr[2].value == 0xFFFFFFFF) ? 0 : ficr[2].value / 1024,
1362-
((ficr[3].value & 0xFF) == 0x00) ? "present" : "not present",
1363-
ficr[4].value,
1364-
ficr[5].value,
1365-
(ficr[6].value == 0xFFFFFFFF) ? 0 : ficr[6].value,
1366-
(ficr[7].value == 0xFFFFFFFF) ? 0 : ficr[7].value,
1367-
(ficr[8].value == 0xFFFFFFFF) ? 0 : ficr[8].value,
1368-
ficr[9].value,
1369-
ficr[10].value, ficr[11].value,
1370-
ficr[12].value, ficr[13].value, ficr[14].value, ficr[15].value,
1371-
ficr[16].value, ficr[17].value, ficr[18].value, ficr[19].value,
1372-
ficr[20].value,
1373-
ficr[21].value, ficr[22].value,
1374-
ficr[23].value,
1375-
ficr[24].value, ficr[25].value, ficr[26].value, ficr[27].value, ficr[28].value,
1376-
ficr[29].value, ficr[30].value, ficr[31].value, ficr[32].value, ficr[33].value,
1377-
(uicr[0].value == 0xFFFFFFFF) ? 0 : uicr[0].value / 1024,
1378-
uicr[1].value & 0xFFFF,
1379-
uicr[2].value & 0xFF,
1380-
uicr[3].value & 0xFFFF);
1381-
1382-
return ERROR_OK;
1383-
}
13841225

13851226
static const struct command_registration nrf5_exec_command_handlers[] = {
13861227
{
@@ -1390,13 +1231,6 @@ static const struct command_registration nrf5_exec_command_handlers[] = {
13901231
.help = "Erase all flash contents of the chip.",
13911232
.usage = "",
13921233
},
1393-
{
1394-
.name = "info",
1395-
.handler = nrf5_handle_info_command,
1396-
.mode = COMMAND_EXEC,
1397-
.help = "Show FICR and UICR info.",
1398-
.usage = "",
1399-
},
14001234
COMMAND_REGISTRATION_DONE
14011235
};
14021236

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