Hi everyone,
I'd like to walk through the process of activating a certain src/dst pip connection manually to get a better feel for what the tool is doing.
To do this I'd like to understand what bits are set (how the configuration frames are built).
Picking an example block, INT_L_X28Y100, and a specific part (Artix-A100T), and a specific endpoint FAN_BOUNCE5->>BYP_ALT1 - how can I check if this pip is active in a bitstream, and the converse - if I want to activate this pip, what does my configuration frame look like?
This particular block is an int_l - going to the database, in the segbits_int_l.db, I find the pip I'd like to activate:
INT_L.BYP_ALT1.FAN_BOUNCE5 21_15 22_15 !23_15 24_15 25_15
Ok, but we need information about where this block is (what bus its connected to, etc) - we get that from the tilegrid.json file, specific to our part:
"INT_L_X28Y100": {
"bits": {
"CLB_IO_CLK": {
"baseaddr": "0x00000E00",
"frames": 28,
"offset": 0,
"words": 2
}
},
"clock_region": "X0Y2",
"grid_x": 70,
"grid_y": 103,
"pin_functions": {},
"prohibited_sites": [],
"sites": {
"TIEOFF_X29Y100": "TIEOFF"
},
"type": "INT_L"
The addressing page indicates how the frames should be built:
We have this table for the 32-bit frame address:
// Edit: Copied table formatting did not work; sorry
| Reserved |
31:26 |
| Bus |
25:23 |
| Top/Bottom Half |
22 |
| Row |
21:17 |
| Column |
16:7 |
| Minor |
6:0 |
But I am having trouble figuring out what the bits will actually look like; it looks like 28 separate frames can configure my tile (https://f4pga.readthedocs.io/projects/prjxray/en/latest/dev_database/part_specific/tilegrid.html). This same page says that an example of absolute frame address calculation can be found in the mask file chapter ( https://f4pga.readthedocs.io/projects/prjxray/en/latest/dev_database/common/mask.html )
I believe the relevant mask file is mask_clbll_l.db, but values in that file go from bit 00_00 to bit 35_63 -> 36 addresses (not 28?). I must have something wrong in my understanding. The documentation states:
The naming scheme for the mask files is the following:
mask_<tile>.db
Then I should be looking for mask_int_l.db, but I do not see this in the prjxray database.
By this point I have confused myself and my head hurts from documentation; any help is greatly appreciated.
Hi everyone,
I'd like to walk through the process of activating a certain src/dst pip connection manually to get a better feel for what the tool is doing.
To do this I'd like to understand what bits are set (how the configuration frames are built).
Picking an example block, INT_L_X28Y100, and a specific part (Artix-A100T), and a specific endpoint FAN_BOUNCE5->>BYP_ALT1 - how can I check if this pip is active in a bitstream, and the converse - if I want to activate this pip, what does my configuration frame look like?
This particular block is an int_l - going to the database, in the segbits_int_l.db, I find the pip I'd like to activate:
INT_L.BYP_ALT1.FAN_BOUNCE5 21_15 22_15 !23_15 24_15 25_15Ok, but we need information about where this block is (what bus its connected to, etc) - we get that from the tilegrid.json file, specific to our part:
The addressing page indicates how the frames should be built:
We have this table for the 32-bit frame address:
// Edit: Copied table formatting did not work; sorry
But I am having trouble figuring out what the bits will actually look like; it looks like 28 separate frames can configure my tile (https://f4pga.readthedocs.io/projects/prjxray/en/latest/dev_database/part_specific/tilegrid.html). This same page says that an example of absolute frame address calculation can be found in the mask file chapter ( https://f4pga.readthedocs.io/projects/prjxray/en/latest/dev_database/common/mask.html )
I believe the relevant mask file is mask_clbll_l.db, but values in that file go from bit 00_00 to bit 35_63 -> 36 addresses (not 28?). I must have something wrong in my understanding. The documentation states:
Then I should be looking for mask_int_l.db, but I do not see this in the prjxray database.
By this point I have confused myself and my head hurts from documentation; any help is greatly appreciated.