Skip to content

Commit c53549e

Browse files
gerbauzdzakhar
gerbauz
authored and
dzakhar
committed
Fixed READMEs for several examples.
1 parent 3eb1abb commit c53549e

File tree

10 files changed

+114
-65
lines changed

10 files changed

+114
-65
lines changed

‎examples/example_cifar10_caffe/README.md‎

Lines changed: 15 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -187,25 +187,25 @@ Console output using provided small test set may look like:
187187
ACCURACY CALCULATION on Input IDX testset according to IDX labels set
188188
IDX test file shape: [20,32,32,3,]
189189
Model input shape: [32,32,3,]
190-
191-
2 of 20 test vectors are processed (2 are correct: 100.000 %)
192-
4 of 20 test vectors are processed (4 are correct: 100.000 %)
193-
6 of 20 test vectors are processed (6 are correct: 100.000 %)
194-
8 of 20 test vectors are processed (8 are correct: 100.000 %)
195-
10 of 20 test vectors are processed (10 are correct: 100.000 %)
196-
12 of 20 test vectors are processed (12 are correct: 100.000 %)
197-
14 of 20 test vectors are processed (14 are correct: 100.000 %)
198-
16 of 20 test vectors are processed (16 are correct: 100.000 %)
199-
18 of 20 test vectors are processed (18 are correct: 100.000 %)
200-
20 of 20 test vectors are processed (20 are correct: 100.000 %)
201-
Final Accuracy: 100.000 % (20 are correct of 20)
190+
191+
2 of 20 test vectors are processed (2 are correct: 100.000 %)
192+
4 of 20 test vectors are processed (4 are correct: 100.000 %)
193+
6 of 20 test vectors are processed (5 are correct: 83.333 %)
194+
8 of 20 test vectors are processed (7 are correct: 87.500 %)
195+
10 of 20 test vectors are processed (9 are correct: 90.000 %)
196+
12 of 20 test vectors are processed (11 are correct: 91.667 %)
197+
14 of 20 test vectors are processed (11 are correct: 78.571 %)
198+
16 of 20 test vectors are processed (13 are correct: 81.250 %)
199+
18 of 20 test vectors are processed (14 are correct: 77.778 %)
200+
20 of 20 test vectors are processed (16 are correct: 80.000 %)
201+
Final Accuracy: 80.000 % (16 are correct of 20)
202202
FINISHED
203203

204204
where:
205-
* `Final Accuracy: 100.000 % (20 are correct of 20)` reflects how many samples from the testset were accurately predicted in comparison with reference label. The accuracy itself may vary depending on the target platform and `run_*` command. In particular :
205+
* `Final Accuracy: 80.000 % (16 are correct of 20)` reflects how many samples from the testset were accurately predicted in comparison with reference label. The accuracy itself may vary depending on the target platform and `run_*` command. In particular :
206206

207-
* `run_FX16` and `run_FX16_FX8_FX8`: Accuracy should be `100.000 %` for provided small test dataset.
208-
* `run_SA8`: Accuracy should be `90.000 %` for provided small test dataset.
207+
* `run_FX16` and `run_FX16_FX8_FX8`: Accuracy should be `80.000 %` for provided small test dataset.
208+
* `run_SA8`: Accuracy should be `75.000 %` for provided small test dataset.
209209

210210
### 3 **External test-set processing.**
211211
Console output using provided small test set should looks mostly the same as for accuracy measurement mode, but without accuracy values.

‎examples/example_cifar10_caffe/small_test_base/labels.idx‎

0 Bytes
Binary file not shown.

‎examples/example_cifar10_caffe/small_test_base/tests.idx‎

0 Bytes
Binary file not shown.

‎examples/example_har_smartphone/README.md‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -156,8 +156,8 @@ where:
156156
* `Result Quality: S/N=5346.3 (74.6 db)` reflects the signal-to-noise ration of the model output in comparison with reference float. The ratio itself (`S/N` and `x db`) may vary depending on the target platform and `run_*` command. In particular :
157157

158158
* `run_FX16`: Result may slightly fluctuates around `S/N=5346.3 (74.6 db)`
159-
* `run_FX16_FX8_FX8`: Result may slightly fluctuates around `S/N=56.0 (35.0 db)`
160159
* `run_SA8`: Result may slightly fluctuates around `S/N=4.6 (13.3 db)`
160+
* `run_FX16_FX8_FX8`: Result may slightly fluctuates around `S/N=56.0 (35.0 db)`
161161

162162
### 2. **Accuracy measurement for testset.**
163163

‎examples/tutorial_emnist_tflm/README.md‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ The first part is disclosed in this readme. The details of the conversion tutori
1010

1111
**Important notes:**
1212

13-
* Example is supported only for VPX configurations with guard bits. For EM/HS, please use [MLI 1.1 release version](https://github.com/foss-for-synopsys-dwc-arc-processors/embarc_mli/tree/Release_1.1/examples/tutorial_emnist_tflm).
13+
* This example can't be built for x86 platform. The example is supported only for VPX configurations with guard bits. For EM/HS, please use [MLI 1.1 release version](https://github.com/foss-for-synopsys-dwc-arc-processors/embarc_mli/tree/Release_1.1/examples/tutorial_emnist_tflm).
1414

1515
## Generate Tensorflow Lite Micro Library
1616

@@ -82,7 +82,7 @@ The first step is to open a command line and change working directory to the roo
8282

8383
1. Build project using generated TCF and appropriate built-in runtime library for it. Use multithreaded build process (4 threads):
8484

85-
gmake TCF_FILE=../../hw/vpx5_integer_full.tcf BUILDLIB_DIR=vpx5_integer_full JOBS=4 build
85+
gmake TCF_FILE=./hw/vpx5_integer_full.tcf BUILDLIB_DIR=vpx5_integer_full JOBS=4 build
8686

8787
1. Change working directory and build the example:
8888

‎user_tests/CMakeLists.txt‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -38,6 +38,10 @@ else()
3838
message(FATAL_ERROR "Rounding mode ${ROUND_MODE} is not supported")
3939
endif()
4040

41+
if (FULL_ACCU STREQUAL ON)
42+
list(APPEND TEST_COMPILE_DEFINITIONS FULL_ACCU_ON)
43+
endif()
44+
4145
# Note: AVEPOOL_16BIT_MUL should be same as the one in mli_lib.cmake
4246
if (NOT DEFINED AVEPOOL_16BIT_MUL)
4347
set(AVEPOOL_16BIT_MUL OFF)

‎user_tests/tests/mli_krn_conv2d/tests_mli_krn_conv2d.cc‎

Lines changed: 16 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -55,23 +55,32 @@ struct conv2d_test_operands {
5555
#if defined(CRC_RM_CONVERGENT) || defined(CRC_RM_UP)
5656

5757
// Shared CRC Results
58-
const crc32_calc test_1_chksum_fx16{ 0x3669E8DA }, test_1_chksum_fx16_fx8_fx8{ 0x627FD168 }, test_1_chksum_sa8{ 0x63A6B2EC },
58+
const crc32_calc test_1_chksum_fx16{ 0x3669E8DA }, test_1_chksum_fx16_fx8_fx8{ 0x627FD168 },
5959
test_2_chksum_fx16{ 0x6075722F }, test_2_chksum_fx16_fx8_fx8{ 0xBFE5DC3D }, test_2_chksum_sa8{ 0x5D288208 },
6060
test_3_chksum_fx16{ 0xE2100158 }, test_3_chksum_fx16_fx8_fx8{ 0x550F135E }, test_3_chksum_sa8{ 0x9740102D },
6161
test_4_chksum_fx16{ 0x987AC0A8 }, test_4_chksum_fx16_fx8_fx8{ 0x21C772CE }, test_4_chksum_sa8{ 0x056EDB56 },
6262
test_5_chksum_fx16{ 0xD8CA1273 }, test_5_chksum_fx16_fx8_fx8{ 0x186AA252 }, test_5_chksum_sa8{ 0x01D390FA },
6363
test_6_chksum_fx16{ 0x150A5D20 },
6464
test_7_chksum_fx16{ 0x05737544 }, test_7_chksum_fx16_fx8_fx8{ 0x7FFA25C2 }, test_7_chksum_sa8{ 0x5E7CF172 },
6565
test_8_chksum_fx16{ 0x69862892 }, test_8_chksum_fx16_fx8_fx8{ 0xA124C817 }, test_8_chksum_sa8{ 0x99E3EE1D },
66-
test_9_chksum_fx16{ 0x3B2662E7 }, test_9_chksum_fx16_fx8_fx8{ 0x5C4D2278 }, test_9_chksum_sa8{ 0x3DB4B9EF },
66+
test_9_chksum_fx16{ 0x3B2662E7 }, test_9_chksum_fx16_fx8_fx8{ 0x5C4D2278 },
6767
test_10_chksum_fx16{ 0x0AD3FF47 }, test_10_chksum_fx16_fx8_fx8{ 0x0CDE9B47 }, test_10_chksum_sa8{ 0xA4EB24F1 },
6868
test_11_chksum_fx16{ 0xEE754246 }, test_11_chksum_fx16_fx8_fx8{ 0x77A6F1AD }, test_11_chksum_sa8{ 0x10AA2F03 };
6969
// Platform Specific CRC Results
70-
#if defined(CRC_RM_UP)
70+
#if defined(FULL_ACCU_ON)
71+
const crc32_calc test_1_chksum_sa8{ 0x63A6B2EC }, test_9_chksum_sa8{ 0x3DB4B9EF };
72+
#else
73+
const crc32_calc test_1_chksum_sa8{ 0xA3FFD976 }, test_9_chksum_sa8{ 0x7D8D9C29 };
74+
#endif
75+
76+
#if defined(CRC_RM_UP) && defined(FULL_ACCU_ON)
77+
const crc32_calc test_6_chksum_fx16_fx8_fx8{ 0x8C24C65A }, test_6_chksum_sa8{ 0x2BA3EA5D };
78+
#elif defined(CRC_RM_UP) && !defined(FULL_ACCU_ON)
7179
const crc32_calc test_6_chksum_fx16_fx8_fx8{ 0x8C24C65A }, test_6_chksum_sa8{ 0x36699F43 };
72-
#else
80+
#else
7381
const crc32_calc test_6_chksum_fx16_fx8_fx8{ 0x0BA52872 }, test_6_chksum_sa8{ 0x2BA3EA5D };
7482
#endif
83+
7584
#else // Not defined CRC_*
7685
const crc32_calc test_1_chksum_fx16, test_1_chksum_fx16_fx8_fx8, test_1_chksum_sa8,
7786
test_2_chksum_fx16, test_2_chksum_fx16_fx8_fx8, test_2_chksum_sa8,
@@ -288,10 +297,10 @@ int main() {
288297
}
289298
#endif
290299

291-
#if V2DSP_XY == V2DSP_XY && defined(CRC_RM_CONVERGENT)
300+
#if PLATFORM == V2DSP_XY && defined(CRC_RM_CONVERGENT)
292301
if (strstr(cur_test->descr, "Test 1 SA8_SA8_SA32") != nullptr ||
293-
strstr(cur_test->descr, "Test 9-1 SA8_SA8_SA32 Dil+Pad") != nullptr ||
294-
strstr(cur_test->descr, "Test 9-2 SA8_SA8_SA32 k3x3 Dil") != nullptr) {
302+
strstr(cur_test->descr, "Test 9-1 SA8_SA8_SA32 Dil+Pad") != nullptr ||
303+
strstr(cur_test->descr, "Test 9-2 SA8_SA8_SA32 k3x3 Dil") != nullptr) {
295304
// Em9d fails bitwise comparison with reference .
296305
reporter.report_message(cur_test->descr, "SKIPPED due to a known issue");
297306
continue;

‎user_tests/tests/mli_krn_depthwise_conv/tests_mli_krn_depthwise_conv.cc‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -61,13 +61,21 @@ const crc32_calc test_1_chksum_fx16{ 0x968FB503 },
6161
test_6_chksum_fx16{ 0xF03253BB }, test_6_chksum_fx16_fx8_fx8{ 0x122832FF }, test_6_chksum_sa8{ 0x42F80E2D },
6262
test_7_chksum_fx16{ 0xDC4EBBE7 }, test_7_chksum_fx16_fx8_fx8{ 0x10447ABF }, test_7_chksum_sa8{ 0xBC318965 },
6363
test_8_chksum_fx16{ 0x4D6EFB91 }, test_8_chksum_sa8{ 0xF888FAB3 },
64-
test_9_chksum_fx16{ 0xBF6D526A }, test_9_chksum_fx16_fx8_fx8{ 0xFB8CEA65 }, test_9_chksum_sa8{ 0xEA5733C6 },
64+
test_9_chksum_fx16{ 0xBF6D526A }, test_9_chksum_fx16_fx8_fx8{ 0xFB8CEA65 },
6565
test_10_chksum_fx16{ 0xC02567E8 }, test_10_chksum_fx16_fx8_fx8{ 0x882F41DB }, test_10_chksum_sa8{ 0x390F7E80 };
6666
// Platform Specific CRC Results
67-
#if defined(CRC_RM_UP)
67+
#if defined(FULL_ACCU_ON)
68+
const crc32_calc test_9_chksum_sa8{ 0xEA5733C6 };
69+
#else
70+
const crc32_calc test_9_chksum_sa8{ 0xE0165E99 };
71+
#endif
72+
73+
#if defined(CRC_RM_UP) && defined(FULL_ACCU_ON)
74+
const crc32_calc test_1_chksum_fx16_fx8_fx8{ 0x46A964A7 }, test_1_chksum_sa8{ 0x46D36646 },
75+
test_8_chksum_fx16_fx8_fx8{ 0xB73234B8 };
76+
#elif defined(CRC_RM_UP) && !defined(FULL_ACCU_ON)
6877
const crc32_calc test_1_chksum_fx16_fx8_fx8{ 0x46A964A7 }, test_1_chksum_sa8{ 0x366725E9 },
6978
test_8_chksum_fx16_fx8_fx8{ 0xB73234B8 };
70-
7179
#else
7280
const crc32_calc test_1_chksum_fx16_fx8_fx8{ 0xA6CC6260 }, test_1_chksum_sa8{ 0x46D36646 },
7381
test_8_chksum_fx16_fx8_fx8{ 0x55734EF0 };
@@ -273,7 +281,7 @@ int main() {
273281
}
274282
#endif
275283

276-
#if V2DSP_XY == V2DSP_XY && defined(CRC_RM_CONVERGENT)
284+
#if PLATFORM == V2DSP_XY && defined(CRC_RM_CONVERGENT)
277285
if (strstr(cur_test->descr, "Test 9 SA8_SA8_SA32 k5x5 Dil") != nullptr) {
278286
// Em9d fails bitwise comparison with reference .
279287
reporter.report_message(cur_test->descr, "SKIPPED due to a known issue");

‎user_tests/tests/mli_krn_group_conv2d/tests_mli_krn_group_conv2d.cc‎

Lines changed: 25 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -56,21 +56,29 @@ struct group_conv2d_test_operands {
5656
#if defined(CRC_RM_CONVERGENT) || defined(CRC_RM_UP)
5757

5858
// Shared CRC Results
59-
const crc32_calc test_1_chksum_fx16{ 0xB782413A }, test_1_chksum_fx16_fx8_fx8{ 0xEE4193A9 }, test_1_chksum_sa8{ 0x11D2D466 },
59+
const crc32_calc test_1_chksum_fx16{ 0xB782413A }, test_1_chksum_fx16_fx8_fx8{ 0xEE4193A9 },
6060
test_2_chksum_fx16{ 0x65FD03D2 }, test_2_chksum_fx16_fx8_fx8{ 0xB34C4A01 }, test_2_chksum_sa8{ 0x33341D2B },
6161
test_3_chksum_fx16{ 0x71B9E656 }, test_3_chksum_fx16_fx8_fx8{ 0x67578BCF }, test_3_chksum_sa8{ 0xAAD727F2 },
62-
test_4_chksum_fx16{ 0x2D7FD678 }, test_4_chksum_fx16_fx8_fx8{ 0x96994E5E }, test_4_chksum_sa8{ 0xCC24BECE },
62+
test_4_chksum_fx16{ 0x2D7FD678 }, test_4_chksum_fx16_fx8_fx8{ 0x96994E5E },
6363
test_5_chksum_fx16{ 0xB719F4A0 }, test_5_chksum_fx16_fx8_fx8{ 0x985577E0 }, test_5_chksum_sa8{ 0xBD32CF0A },
6464
test_6_chksum_fx16{ 0x3013D414 }, test_6_chksum_fx16_fx8_fx8{ 0xCB153206 }, test_6_chksum_sa8{ 0xC61C378D },
6565
test_7_chksum_fx16{ 0xC979FA6E }, test_7_chksum_fx16_fx8_fx8{ 0x5D29B6B4 }, test_7_chksum_sa8{ 0x28AFE63F },
6666
test_8_chksum_fx16{ 0xAC7AFCAE }, test_8_chksum_sa8{ 0xE97450E4 },
6767
test_9_chksum_fx16{ 0x2DDBDF54 }, test_9_chksum_fx16_fx8_fx8{ 0x575372E7 },
68-
test_10_chksum_fx16{ 0x78039E74 }, test_10_chksum_fx16_fx8_fx8{ 0x1783EEEC }, test_10_chksum_sa8{ 0x3685F72F };
68+
test_10_chksum_fx16{ 0x78039E74 }, test_10_chksum_fx16_fx8_fx8{ 0x1783EEEC };
6969
// Platform Specific CRC Results
70-
#if defined(CRC_RM_UP)
71-
const crc32_calc test_8_chksum_fx16_fx8_fx8{ 0x629A3BD0 }, test_9_chksum_sa8{ 0x38F5EB92 };
70+
#if defined(FULL_ACCU_ON)
71+
const crc32_calc test_1_chksum_sa8{ 0x11D2D466 }, test_10_chksum_sa8{ 0x3685F72F };
72+
#else
73+
const crc32_calc test_1_chksum_sa8{ 0xB0EBD3DC }, test_10_chksum_sa8{ 0x079DC058 };
74+
#endif
75+
76+
#if defined(CRC_RM_UP) && defined(FULL_ACCU_ON)
77+
const crc32_calc test_8_chksum_fx16_fx8_fx8{ 0x629A3BD0 }, test_9_chksum_sa8{ 0x38F5EB92 }, test_4_chksum_sa8{ 0xE5DBC862 };
78+
#elif defined(CRC_RM_UP) && !defined(FULL_ACCU_ON)
79+
const crc32_calc test_8_chksum_fx16_fx8_fx8{ 0x629A3BD0 }, test_9_chksum_sa8{ 0x38F5EB92 }, test_4_chksum_sa8{ 0xCC24BECE };
7280
#else
73-
const crc32_calc test_8_chksum_fx16_fx8_fx8{ 0x0597C4DB }, test_9_chksum_sa8{ 0x396D8D7A };
81+
const crc32_calc test_8_chksum_fx16_fx8_fx8{ 0x0597C4DB }, test_9_chksum_sa8{ 0x396D8D7A }, test_4_chksum_sa8{ 0xCC24BECE };
7482
#endif
7583
#else // Not defined CRC_*
7684
const crc32_calc test_1_chksum_fx16, test_1_chksum_fx16_fx8_fx8, test_1_chksum_sa8,
@@ -290,24 +298,24 @@ int main() {
290298

291299
#if defined(__Xvec_guard_bit_option) && (__Xvec_guard_bit_option == 0)
292300
if (strstr(cur_test->descr, "Test 1 FX16") != nullptr ||
293-
strstr(cur_test->descr, "Test 2 FX16 ReluGen") != nullptr ||
294-
strstr(cur_test->descr, "Test 3 SA8_SA8_SA32 Mult FPG") != nullptr ||
295-
strstr(cur_test->descr, "Test 4 FX16 DW call") != nullptr ||
296-
strstr(cur_test->descr, "Test 5 FX16 Conv2D call") != nullptr ||
297-
strstr(cur_test->descr, "Test 6 FX16 IO_Memstr") != nullptr ||
298-
strstr(cur_test->descr, "Test 7 FX16 W_Memstr") != nullptr ||
299-
strstr(cur_test->descr, "Test 9 FX16 k3x3 Mstr+Dil") != nullptr ||
300-
strstr(cur_test->descr, "Test 10 FX16 k5x5 Mstr+Dil") != nullptr ||
301-
strstr(cur_test->descr, "Test 10 SA8 k5x5 Mstr+Dil") != nullptr) {
301+
strstr(cur_test->descr, "Test 2 FX16 ReluGen") != nullptr ||
302+
strstr(cur_test->descr, "Test 3 SA8_SA8_SA32 Mult FPG") != nullptr ||
303+
strstr(cur_test->descr, "Test 4 FX16 DW call") != nullptr ||
304+
strstr(cur_test->descr, "Test 5 FX16 Conv2D call") != nullptr ||
305+
strstr(cur_test->descr, "Test 6 FX16 IO_Memstr") != nullptr ||
306+
strstr(cur_test->descr, "Test 7 FX16 W_Memstr") != nullptr ||
307+
strstr(cur_test->descr, "Test 9 FX16 k3x3 Mstr+Dil") != nullptr ||
308+
strstr(cur_test->descr, "Test 10 FX16 k5x5 Mstr+Dil") != nullptr ||
309+
strstr(cur_test->descr, "Test 10 SA8 k5x5 Mstr+Dil") != nullptr) {
302310
// VPX fails bitwise comparison with reference .
303311
reporter.report_message(cur_test->descr, "SKIPPED due to a known issue");
304312
continue;
305313
}
306314
#endif
307315

308-
#if V2DSP_XY == V2DSP_XY && defined(CRC_RM_CONVERGENT)
316+
#if PLATFORM == V2DSP_XY && defined(CRC_RM_CONVERGENT)
309317
if (strstr(cur_test->descr, "Test 1 SA8_SA8_SA32") != nullptr ||
310-
strstr(cur_test->descr, "Test 10 SA8 k5x5 Mstr+Dil") != nullptr) {
318+
strstr(cur_test->descr, "Test 10 SA8 k5x5 Mstr+Dil") != nullptr) {
311319
// Em9d fails bitwise comparison with reference .
312320
reporter.report_message(cur_test->descr, "SKIPPED due to a known issue");
313321
continue;

0 commit comments

Comments
 (0)