arcv: apex: Add "i" suffix to resolved immediate-format instructions.

luismgsilva · luismgsilva · commit 045bf671cdf8 · 2025-07-22T06:20:36.000-07:00
When an APEX instruction does not have a user-defined format specified
via pragma, its format is resolved based on operand flags and opcode.  In
these cases, this patch appends an "i" suffix to the instruction name to
distinguish it from the XD format.  While XD instructions and
immediate-based formats (XI, XS, XC) may have the same number of
operands, XD uses only registers, whereas the others include at least
one immediate operand.

Signed-off-by: Luis Silva &lt;luiss@synopsys.com&gt;
diff --git a/gcc/config/riscv/arcv-apex.md b/gcc/config/riscv/arcv-apex.md
@@ -51,11 +51,13 @@
   ""
 {
   const char *str = arcv_apex_get_insn_name (operands[0]);
+  const char *suffix = arcv_apex_get_insn_suffix (operands[0]);
   switch (which_alternative)
   {
     case 0:
-      return xasprintf ("%si\t%d ; 'XI' `insn src0`",
+      return xasprintf ("%s%s\t%d ; 'XI' `insn src0`",
 			str,
+			suffix,
 			(int) INTVAL (operands[1]));
     case 1:
       return xasprintf ("%s\t%s ; 'XD' `insn src0`",
@@ -96,11 +98,13 @@
   ""
 {
   const char *str = arcv_apex_get_insn_name (operands[0]);
+  const char *suffix = arcv_apex_get_insn_suffix (operands[0]);
   switch (which_alternative)
   {
     case 0:
-      return xasprintf ("%si\t%s,%d ; 'XS' `insn src0, src1`",
+      return xasprintf ("%s%s\t%s,%d ; 'XS' `insn src0, src1`",
 			str,
+			suffix,
 			reg_names[REGNO (operands[1])],
 			(int) INTVAL (operands[2]));
     case 1:
@@ -213,11 +217,13 @@
   ""
 {
   const char *str = arcv_apex_get_insn_name (operands[1]);
+  const char *suffix = arcv_apex_get_insn_suffix (operands[1]);
   switch (which_alternative)
   {
     case 0:
-      return xasprintf ("%si\t%s,%d ; 'XI' `insn des, src0` volatile",
+      return xasprintf ("%s%s\t%s,%d ; 'XI' `insn des, src0` volatile",
 			str,
+			suffix,
 			reg_names[REGNO (operands[0])],
 			(int) INTVAL (operands[2]));
     case 1:
@@ -262,11 +268,13 @@
   ""
 {
   const char *str = arcv_apex_get_insn_name (operands[1]);
+  const char *suffix = arcv_apex_get_insn_suffix (operands[1]);
   switch (which_alternative)
   {
     case 0:
-      return xasprintf ("%si\t%s,%d ; 'XI' `insn des, src0`",
+      return xasprintf ("%s%s\t%s,%d ; 'XI' `insn des, src0`",
 			str,
+			suffix,
 			reg_names[REGNO (operands[0])],
 			(int) INTVAL (operands[2]));
     case 1:
@@ -312,17 +320,20 @@
   ""
 {
   const char *str = arcv_apex_get_insn_name (operands[1]);
+  const char *suffix = arcv_apex_get_insn_suffix (operands[1]);
   switch (which_alternative)
   {
     case 0:
-      return xasprintf ("%si\t%s,%s,%d ; 'XS' `insn dest, src0, imm/src1` volatile",
+      return xasprintf ("%s%s\t%s,%s,%d ; 'XS' `insn dest, src0, imm/src1` volatile",
 			str,
+			suffix,
 			reg_names[REGNO (operands[0])],
 			reg_names[REGNO (operands[2])],
 			(int) INTVAL (operands[3]));
     case 1:
       return xasprintf ("%s%s\t%s,%s,%d ; 'XC' `insn dest/src0, imm` volatile",
 			str,
+			suffix,
 			reg_names[REGNO (operands[0])],
 			reg_names[REGNO (operands[2])],
 			(int) INTVAL (operands[3]));
@@ -372,17 +383,20 @@
   ""
 {
   const char *str = arcv_apex_get_insn_name (operands[1]);
+  const char *suffix = arcv_apex_get_insn_suffix (operands[1]);
   switch (which_alternative)
   {
     case 0:
-      return xasprintf ("%si\t%s,%s,%d ; 'XS' `insn dest, src0, imm/src1`",
+      return xasprintf ("%s%s\t%s,%s,%d ; 'XS' `insn dest, src0, imm/src1`",
 			str,
+			suffix,
 			reg_names[REGNO (operands[0])],
 			reg_names[REGNO (operands[2])],
 			(int) INTVAL (operands[3]));
     case 1:
       return xasprintf ("%s%s\t%s,%s,%d ; 'XC' `insn dest/src0, imm`",
 			str,
+			suffix,
 			reg_names[REGNO (operands[0])],
 			reg_names[REGNO (operands[2])],
 			(int) INTVAL (operands[3]));
diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc
@@ -253,6 +253,10 @@ struct arcv_apex_builtin_description {
   /* Specifies the instruction format.  See "apex_insn_format" enum
     for more details.  */
   unsigned int insn_formats;
+
+  /* Suffix added to the instruction name when the format is resolved
+      (e.g., XS, XI, or XC); set to "i" if resolved, otherwise "".  */
+  const char *insn_suffix;
 };
 
 /* The XD-type has 8 function bits encoding up to 256 instructions.
@@ -598,6 +602,18 @@ arcv_apex_get_insn_name (rtx op)
   return arcv_apex_builtins[subcode].insn_name;
 }
 
+/* Return the instruction suffix for an APEX subcode operand.
+
+   This suffix is used to mark instructions whose format was resolved
+   (e.g., XS, XI, or XC) rather than explicitly specified via pragma.  */
+
+const char*
+arcv_apex_get_insn_suffix (rtx op)
+{
+  unsigned int subcode = UINTVAL (op);
+  return arcv_apex_builtins[subcode].insn_suffix;
+}
+
 /* Checks if the APEX builtin instruction identified by the subcode
    supports the given instruction format.
 
@@ -716,10 +732,6 @@ arcv_apex_set_insn_operand_flags (unsigned int insn_format, tree fndecl)
 static unsigned int
 arcv_apex_resolve_insn_format (unsigned int insn_format, unsigned int opcode)
 {
-  /* Return early if a instruction format was defined by the used.  */
-  if ((insn_format & 0xF) != APEX_NONE)
-    return insn_format;
-
   /* Extract the operand flags (DEST, SRC0, SRC1) from bits 5–7.
      These bits encode the operand signature used for format selection.  */
   unsigned int insn_operands = insn_format >> 5;
@@ -933,15 +945,21 @@ arcv_apex_init_builtin (tree fndecl, const char *fn_name,
 
   /* Resolve the instruction format:
      If the user did not specify an instruction format at pragma level,
-     infer the concrete format based on opcode and operand flags; otherwise,
-     leave it as is.  */
-  insn_formats = arcv_apex_resolve_insn_format (insn_formats, opcode);
+     infer the concrete format based on opcode and operand flags.  Mark
+     the insn. name with an "i" suffix for resolved XS/XI/XC formats;
+     otherwise, leave it as is.  */
+  const char *insn_suffix = "";
+  if ((insn_formats & 0xF) == APEX_NONE)
+  {
+    insn_formats = arcv_apex_resolve_insn_format (insn_formats, opcode);
+    insn_suffix = "i";
+  }
 
   /* Validate the format is allowed for this instruction.  */
   arcv_apex_validate_insn_format (fn_name, insn_formats, opcode);
 
   /* Print .extInstruction section about APEX instruction.  */
-  arcv_apex_print_insn_section (insn_name, opcode, insn_formats);
+  arcv_apex_print_insn_section (insn_name, insn_suffix, opcode, insn_formats);
 
   /* Determine the internal instruction code (icode).  */
   enum insn_code icode = arcv_apex_get_icode (insn_formats);
@@ -953,7 +971,7 @@ arcv_apex_init_builtin (tree fndecl, const char *fn_name,
 
   /* Store APEX insn information.  */
   arcv_apex_builtins[arcv_apex_builtin_index]
-	= { icode, fn_name, insn_name, builtin_type, insn_formats };
+    = { icode, fn_name, insn_name, builtin_type, insn_formats, insn_suffix };
 
   /* Modify the prototype type as built-in.  */
   fndecl->function_decl.built_in_class = BUILT_IN_MD;
diff --git a/gcc/config/riscv/riscv-protos.h b/gcc/config/riscv/riscv-protos.h
@@ -770,8 +770,10 @@ extern bool riscv_is_micro_arch (enum riscv_microarchitecture_type);
 
 extern bool arcv_micro_arch_supports_fusion_p (void);
 
-extern void arcv_apex_print_insn_section (const char *, int, unsigned int);
+extern void arcv_apex_print_insn_section (const char *, const char *,
+					  int, unsigned int);
 extern const char* arcv_apex_get_insn_name (rtx);
+extern const char* arcv_apex_get_insn_suffix (rtx);
 extern bool arcv_apex_format_supports_p (unsigned int, unsigned int);
 extern void arcv_apex_init_builtin (tree, const char *, const char *,
 				    unsigned int, int);
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
@@ -9693,8 +9693,8 @@ riscv_asm_output_variant_cc (FILE *stream, const tree decl, const char *name)
   and source1.  */
 
 void
-arcv_apex_print_insn_section (const char *insn_name, int opcode,
-			      unsigned int insn_format)
+arcv_apex_print_insn_section (const char *insn_name, const char *insn_suffix,
+			      int opcode, unsigned int insn_format)
 {
   /* Extract the operand flags (DEST, SRC0, SRC1) from bits 5–7.
      These bits encode the operand signature used for format selection.  */
@@ -9718,7 +9718,8 @@ arcv_apex_print_insn_section (const char *insn_name, int opcode,
   if ((insn_format & (APEX_XS | APEX_XC))
 	&& (insn_operands == APEX_DEST_FTYPE_SRC0_SRC1))
   {
-    fprintf (asm_out_file, "\t.extInstruction %si,%d", insn_name, opcode);
+    fprintf (asm_out_file, "\t.extInstruction %s%s,%d",
+	     insn_name, insn_suffix, opcode);
     if (insn_format & APEX_XS)
       fputs (",XS", asm_out_file);
     if (insn_format & APEX_XC)
@@ -9729,7 +9730,8 @@ arcv_apex_print_insn_section (const char *insn_name, int opcode,
   /* Print XI format with dest, src0 operands; append ",void" if no dest.  */
   if (insn_format & APEX_XI)
   {
-    fprintf (asm_out_file, "\t.extInstruction %si,%d,XI", insn_name, opcode);
+    fprintf (asm_out_file, "\t.extInstruction %s%s,%d,XI",
+	     insn_name, insn_suffix, opcode);
     if ((insn_format & APEX_DEST) == 0)
       fputs (",void", asm_out_file);
     fputc ('\n', asm_out_file);
@@ -9739,8 +9741,8 @@ arcv_apex_print_insn_section (const char *insn_name, int opcode,
   if ((insn_format & APEX_XS)
 	&& (insn_operands == APEX_VOID_FTYPE_SRC0_SRC1))
   {
-    fprintf (asm_out_file, "\t.extInstruction %si,%d,XS,void\n",
-			insn_name, opcode);
+    fprintf (asm_out_file, "\t.extInstruction %s%s,%d,XS,void\n",
+			insn_name, insn_suffix, opcode);
   }
 }
 
