arcv: apex: Add subcode operand to APEX RTX instructions.

This patch extends "riscv_expand_builtin_direct" to optionally accept
and attach a subcode operand for APEX builtins. A new "has_subcode_p"
flag determines whether a constant RTL operand for the subcode should
be added to the operand list.

The subcode is used to extract the instruction name from
"arcv_apex_builtins" once a pattern is selected in the machine description
(see "arcv_apex_get_insn_name (rtx op)").

Also updates "riscv_check_builtin_call" and
"riscv_resolve_overloaded_builtin" to handle the new
"RISCV_BUILTIN_APEX" class.

Signed-off-by: Luis Silva <[email protected]>

Author: luismgsilva

gcc/config/riscv/riscv-builtins.cc

@@ -389,7 +389,8 @@ riscv_expand_builtin_insn (enum insn_code icode, unsigned int n_ops,
 
 static rtx
 riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
-			     bool has_target_p)
+			     bool has_target_p, unsigned int subcode,
+			     bool has_subcode_p)
 {
   struct expand_operand ops[MAX_RECOG_OPERANDS];
 
@@ -398,6 +399,14 @@ riscv_expand_builtin_direct (enum insn_code icode, rtx target, tree exp,
   if (has_target_p)
     create_output_operand (&ops[opno++], target, TYPE_MODE (TREE_TYPE (exp)));
 
+  if (has_subcode_p)
+  {
+    /* Create an RTL constant for the APEX subcode.  */
+    rtx const_rtx = GEN_INT (subcode);
+    /* Add the subcode as an additional input operand to the RTL expression.  */
+    create_input_operand (&ops[opno++], const_rtx, SImode);
+  }
+
   /* Map the arguments to the other operands.  */
   gcc_assert (opno + call_expr_nargs (exp)
 	      == insn_data[icode].n_generator_args);
@@ -449,16 +458,34 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED,
     {
       case RISCV_BUILTIN_VECTOR:
 	return riscv_vector::expand_builtin (subcode, exp, target);
+      case RISCV_BUILTIN_APEX: {
+	const struct arcv_apex_builtin_description *d
+		= &arcv_apex_builtins[subcode];
+
+	switch (d->builtin_type)
+	  {
+	  case RISCV_BUILTIN_DIRECT:
+	    return riscv_expand_builtin_direct (d->icode, target, exp, true,
+						subcode, true);
+
+	  case RISCV_BUILTIN_DIRECT_NO_TARGET:
+	    return riscv_expand_builtin_direct (d->icode, target, exp, false,
+						subcode, true);
+	  }
+	break;
+      }
       case RISCV_BUILTIN_GENERAL: {
 	const struct riscv_builtin_description *d = &riscv_builtins[subcode];
 
 	switch (d->builtin_type)
 	  {
 	  case RISCV_BUILTIN_DIRECT:
-	    return riscv_expand_builtin_direct (d->icode, target, exp, true);
+	    return riscv_expand_builtin_direct (d->icode, target, exp, true,
+						subcode, false);
 
 	  case RISCV_BUILTIN_DIRECT_NO_TARGET:
-	    return riscv_expand_builtin_direct (d->icode, target, exp, false);
+	    return riscv_expand_builtin_direct (d->icode, target, exp, false,
+						subcode, false);
 	  }
       }
     }

gcc/config/riscv/riscv-c.cc

@@ -524,6 +524,9 @@ riscv_check_builtin_call (location_t loc, vec<location_t> arg_loc, tree fndecl,
     case RISCV_BUILTIN_VECTOR:
       return riscv_vector::check_builtin_call (loc, arg_loc, subcode,
 					       fndecl, nargs, args);
+
+    case RISCV_BUILTIN_APEX:
+      return true;
     }
   gcc_unreachable ();
 }
@@ -551,6 +554,8 @@ riscv_resolve_overloaded_builtin (unsigned int uncast_location, tree fndecl,
       new_fndecl = riscv_vector::resolve_overloaded_builtin (loc, subcode,
 							     fndecl, arglist);
       break;
+    case RISCV_BUILTIN_APEX:
+      break;
     default:
       gcc_unreachable ();
     }