@@ -5250,21 +5250,38 @@ arc_function_args_impl (CUMULATIVE_ARGS *cum,
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{
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reg_idx = cum -> last_reg ; /* for unamed args don't try fill up the reg-holes. */
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nregs = arc_hard_regno_nregs (0 , mode , type ); /* only interested in the number of regs. */
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- if ((nregs == 2 )
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+ if ((( nregs == 2 ) || ( nregs == 4 ) )
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&& (mode != BLKmode ) /* Only DI-like modes are interesting for us. */
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&& (reg_idx & 1 ) /* Only for "non-aligned" registers. */
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&& FUNCTION_ARG_REGNO_P (reg_idx )) /* Allow passing partial arguments. */
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{
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- rtx reg1 = gen_rtx_REG (SImode , reg_idx );
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- rtx reg2 = gen_rtx_REG (SImode , reg_idx + 1 );
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- rtvec vec = gen_rtvec (2 , gen_rtx_EXPR_LIST (VOIDmode , reg1 , const0_rtx ),
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- gen_rtx_EXPR_LIST (VOIDmode , reg2 , GEN_INT (4 )));
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+ rtx reg [4 ];
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+ rtvec vec ;
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+
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+ if (nregs == 2 )
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+ {
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+ reg [0 ] = gen_rtx_REG (SImode , reg_idx );
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+ reg [1 ] = gen_rtx_REG (SImode , reg_idx + 1 );
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+ vec = gen_rtvec (2 , gen_rtx_EXPR_LIST (VOIDmode , reg [0 ], const0_rtx ),
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+ gen_rtx_EXPR_LIST (VOIDmode , reg [1 ], GEN_INT (4 )));
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+ }
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+ else
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+ {
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+ reg [0 ] = gen_rtx_REG (SImode , reg_idx );
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+ reg [1 ] = gen_rtx_REG (SImode , reg_idx + 1 );
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+ reg [2 ] = gen_rtx_REG (SImode , reg_idx + 2 );
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+ reg [3 ] = gen_rtx_REG (SImode , reg_idx + 3 );
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+ vec = gen_rtvec (4 , gen_rtx_EXPR_LIST (VOIDmode , reg [0 ], const0_rtx ),
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+ gen_rtx_EXPR_LIST (VOIDmode , reg [1 ], GEN_INT (4 )),
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+ gen_rtx_EXPR_LIST (VOIDmode , reg [2 ], GEN_INT (8 )),
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+ gen_rtx_EXPR_LIST (VOIDmode , reg [3 ], GEN_INT (12 )));
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+ }
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if (advance )
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{
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cum -> arg_num += nregs ;
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- cum -> avail [ reg_idx ] = false;
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- cum -> avail [reg_idx + 1 ] = false;
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+ for ( int i = 0 ; i < nregs ; i ++ )
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+ cum -> avail [reg_idx + i ] = false;
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cum -> last_reg += nregs ;
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}
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