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Siyuan Cheng
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arc: add nsim_em11d target
add nsim_em11d target specific for DSP feature Signed-off-by: Siyuan Cheng <[email protected]>
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‎boards/arc/nsim/doc/index.rst

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@@ -18,13 +18,15 @@ There are four supported board sub-configurations:
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* ``nsim_em`` which includes normal ARC EM features and ARC MPUv2
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* ``nsim_em_em7d_v22`` which includes normal ARC EM features and ARC MPUv2, specially with one register bank and fast irq
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* ``nsim_em_em11d`` which includes normal ARC EM features and ARC MPUv2, specially with XY memory and DSP feature.
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* ``nsim_sem`` which includes secure ARC EM features and ARC MPUv3
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* ``nsim_hs`` which includes base ARC HS features, i.e. w/o PMU and MMU
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* ``nsim_hs_smp`` which includes base ARC HS features in multi-core cluster, still w/o PMU and MMU
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For detailed arc features, please refer to
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:zephyr_file:`boards/arc/nsim/support/nsim_em.props`,
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:zephyr_file:`boards/arc/nsim/support/nsim_em7d_v22.props`,
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:zephyr_file:`boards/arc/nsim/support/nsim_em11d.props`,
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:zephyr_file:`boards/arc/nsim/support/nsim_sem.props`,
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:zephyr_file:`boards/arc/nsim/support/nsim_hs.props` and
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:zephyr_file:`boards/arc/nsim/support/mdb_hs_smp.args`

‎boards/arc/nsim/nsim_em11d.dts

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/*
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* Copyright (c) 2022 Synopsys, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include "nsim_em.dtsi"
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#define XCCM_ADDR c0000000
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#define XCCM_SIZE DT_SIZE_K(64)
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#define YCCM_ADDR e0000000
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#define YCCM_SIZE DT_SIZE_K(64)
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/ {
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model = "snps,nsim_em";
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compatible = "snps,nsim_em";
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xccm0: xccm@XCCM_ADDR {
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compatible = "arc,xccm";
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reg = <DT_ADDR(XCCM_ADDR) XCCM_SIZE>;
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};
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yccm0: yccm@YCCM_ADDR {
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compatible = "arc,yccm";
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reg = <DT_ADDR(YCCM_ADDR) YCCM_SIZE>;
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};
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};
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&cpu0 {
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clock-frequency = <5000000>;
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};

‎boards/arc/nsim/nsim_em11d.yaml

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identifier: nsim_em11d
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name: EM11D Nsim simulator
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type: mcu
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simulation: nsim
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arch: arc
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toolchain:
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- arcmwdt
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testing:
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ignore_tags:
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- net
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- bluetooth

‎boards/arc/nsim/nsim_em11d_defconfig

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_SOC_NSIM=y
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CONFIG_SOC_NSIM_EM11D=y
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CONFIG_BOARD_NSIM=y
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
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CONFIG_XIP=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_ARCV2_INTERRUPT_UNIT=y
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CONFIG_ARCV2_TIMER=y
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CONFIG_ARC_MPU_ENABLE=y
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CONFIG_CONSOLE=y
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CONFIG_UART_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_ARC_EXCEPTION_DEBUG=y
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CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y

‎boards/arc/nsim/support/mdb_em11d.args

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-arcv2em
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-core3
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-rgf_num_banks=2
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-rgf_banked_regs=32
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-rgf_num_wr_ports=2
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-Xcode_density
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-Xdiv_rem=radix2
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-turbo_boost
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-Xswap
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-Xbitscan
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-Xmpy_option=mpyd
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-mpu
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-mpu_regions=16
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-Xshift_assist
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-Xbarrel_shifter
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-Xdsp2
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-Xdsp_complex
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-Xdsp_divsqrt=radix2
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-Xdsp_itu
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-Xdsp_accshift=full
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-Xagu_large
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-Xagu_wb_depth=4
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-Xagu_accord
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-Xxy
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-Xxy_config=dccm_x_y
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-Xxy_size=64K
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-Xxy_interleave
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-Xxy_x_base=0xc0000000
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-Xxy_y_base=0xe0000000
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-Xfpus_div
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-Xfpu_mac
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-Xfpuda
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-Xfpus_mpy_slow
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-Xfpus_div_slow
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-Xtimer0
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-Xtimer0_level=1
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-Xtimer1
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-Xtimer1_level=0
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-action_points=2
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-Xstack_check
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-dmp_peripheral
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-smart_stack_entries=8
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-interrupts=20
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-interrupt_priorities=4
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-ext_interrupts=16
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-firq
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-interrupt_base=0x0
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-dcache=16384,32,2,a
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-dcache_feature=2
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-icache=16384,32,2,a
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-icache_feature=2
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-dccm_size=0x100000
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-dccm_base=0x80000000
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-dccm_interleave
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-iccm0_size=0x100000
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-iccm0_base=0x00000000
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-Xpct_counters=8
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-dmac
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-dmac_channels=2
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-dmac_registers=0
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-dmac_fifo_depth=2
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-dmac_int_config=single_internal
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-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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-noprofile
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-Xunaligned

‎boards/arc/nsim/support/nsim_em11d.props

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nsim_isa_family=av2em
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nsim_isa_core=3
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arcver=0x3
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nsim_isa_rgf_num_banks=2
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nsim_isa_rgf_banked_regs=32
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nsim_isa_rgf_num_regs=32
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nsim_isa_rgf_num_wr_ports=2
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nsim_isa_big_endian=0
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nsim_isa_lpc_size=32
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nsim_isa_pc_size=32
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nsim_isa_addr_size=32
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nsim_isa_code_density_option=2
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nsim_isa_div_rem_option=1
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nsim_isa_turbo_boost=1
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nsim_isa_swap_option=1
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nsim_isa_bitscan_option=1
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nsim_isa_mpy_option=8
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nsim_isa_shift_option=3
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mpu_regions=16
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mpu_version=2
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nsim_isa_dsp_option=2
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nsim_isa_dsp_complex_option=1
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nsim_isa_dsp_divsqrt_option=1
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nsim_isa_dsp_itu_option=1
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nsim_isa_dsp_itu_option=1
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nsim_isa_dsp_accshift_option=2
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nsim_isa_agu_size=large
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nsim_isa_agu_wb_depth=4
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nsim_isa_agu_accord=1
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nsim_isa_xy=1
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nsim_isa_xy_config=dccm_x_y
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nsim_isa_xy_size=64K
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nsim_isa_xy_interleave=1
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nsim_isa_xy_x_base=0xc0000000
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nsim_isa_xy_y_base=0xe0000000
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nsim_isa_fpus_div_option=1
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nsim_isa_fpu_mac_option=1
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nsim_isa_fpuda_option=1
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nsim_isa_fpu_fast_mpy_option=0
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nsim_isa_fpu_fast_div_option=0
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nsim_isa_bitstream_option=1
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nsim_isa_enable_timer_0=1
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nsim_isa_timer_0_int_level=1
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nsim_isa_enable_timer_1=1
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nsim_isa_timer_1_int_level=0
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nsim_isa_num_actionpoints=2
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nsim_isa_stack_checking=1
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nsim_isa_has_dmp_peripheral=1
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nsim_isa_smart_stack_entries=8
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nsim_isa_number_of_interrupts=20
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nsim_isa_number_of_levels=4
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nsim_isa_number_of_external_interrupts=16
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nsim_isa_fast_irq=1
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nsim_isa_intvbase_preset=0x0
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dcache=16384,32,2,a
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nsim_isa_dc_feature_level=2
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icache=16384,32,2,a
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nsim_isa_ic_feature_level=2
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dccm_size=0x100000
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dccm_base=0x80000000
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nsim_isa_dccm_interleave=1
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iccm0_size=0x100000
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iccm0_base=0x00000000
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nsim_isa_pct_counters=8
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nsim_isa_dmac_option=1
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nsim_isa_dmac_channels=2
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nsim_isa_dmac_registers=0
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nsim_isa_dmac_fifo_depth=2
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nsim_isa_dmac_int_config=single_internal
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nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
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nsim_isa_unaligned_option=1

‎soc/arc/snps_nsim/CMakeLists.txt

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-Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
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-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
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zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM11D -arcv2em -core3 -Xdiv_rem=radix2
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-Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter
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-Xshift_assist -Xdsp2 -Xdsp_complex -Xxy -Xagu_large
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-Xdsp_ctrl=postshift,noguard,convergent -Hfxapi
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-Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full
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-Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
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-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
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zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_SEM -arcv2em -core3 -Xcode_density
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-Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd
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-Xshift_assist -Xbarrel_shifter -Xdsp2

‎soc/arc/snps_nsim/Kconfig

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select CPU_HAS_MPU
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select CPU_HAS_FPU
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config SOC_NSIM_EM11D
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bool "Synopsys ARC EM11D in nSIM"
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select CPU_HAS_MPU
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select CPU_HAS_DSP
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config SOC_NSIM_SEM
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bool "Synopsys ARC SEM in nSIM"
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select CPU_HAS_MPU

‎soc/arc/snps_nsim/Kconfig.defconfig

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default n
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source "soc/arc/snps_nsim/Kconfig.defconfig.em"
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source "soc/arc/snps_nsim/Kconfig.defconfig.em11d"
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source "soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22"
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source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
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source "soc/arc/snps_nsim/Kconfig.defconfig.hs"

‎soc/arc/snps_nsim/Kconfig.defconfig.em11d

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# Copyright (c) 2022 Synopsys, Inc. All rights reserved.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_NSIM_EM11D
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config CPU_EM6
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default y
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config NUM_IRQ_PRIO_LEVELS
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# This processor supports 4 priority levels:
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# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
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default 4
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config NUM_IRQS
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# must be > the highest interrupt number used
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default 30
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config ARC_MPU_VER
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default 2
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config RGF_NUM_BANKS
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default 2
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 5000000
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config HARVARD
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default y
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config ARC_FIRQ
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default y
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config CACHE_MANAGEMENT
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default y
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config FP_FPU_DA
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default y
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if (ARC_MPU_VER = 2)
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config MAIN_STACK_SIZE
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default 2048
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config IDLE_STACK_SIZE
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default 2048
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config ZTEST_STACK_SIZE
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default 2048
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depends on ZTEST
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endif # ARC_MPU_VER
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config ARC_HAS_ACCL_REGS
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default y
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config ARC_HAS_AGU_REGS
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default y
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config AGU_SHARING
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default y
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config ARC_AGU_LARGE
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default y
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endif # SOC_NSIM_EM11D

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