@@ -24,8 +24,7 @@ mod pl011;
2424mod pl031;
2525
2626use crate :: pl031:: Rtc ;
27- use arm_gic:: gicv3:: { IntId , Trigger } ;
28- use arm_gic:: { irq_enable, wfi} ;
27+ use arm_gic:: { irq_enable, wfi, IntId , Trigger } ;
2928use chrono:: { TimeZone , Utc } ;
3029use core:: hint:: spin_loop;
3130// ANCHOR: imports
@@ -63,8 +62,9 @@ extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
6362 // SAFETY: `GICD_BASE_ADDRESS` and `GICR_BASE_ADDRESS` are the base
6463 // addresses of a GICv3 distributor and redistributor respectively, and
6564 // nothing else accesses those address ranges.
66- let mut gic = unsafe { GicV3 :: new ( GICD_BASE_ADDRESS , GICR_BASE_ADDRESS ) } ;
67- gic. setup ( ) ;
65+ let mut gic =
66+ unsafe { GicV3 :: new ( GICD_BASE_ADDRESS , GICR_BASE_ADDRESS , 1 , 0x20000 ) } ;
67+ gic. setup ( 0 ) ;
6868 // ANCHOR_END: main
6969
7070 // SAFETY: `PL031_BASE_ADDRESS` is the base address of a PL031 device, and
@@ -75,10 +75,10 @@ extern "C" fn main(x0: u64, x1: u64, x2: u64, x3: u64) {
7575 info ! ( "RTC: {time}" ) ;
7676
7777 GicV3 :: set_priority_mask ( 0xff ) ;
78- gic. set_interrupt_priority ( PL031_IRQ , 0x80 ) ;
79- gic. set_trigger ( PL031_IRQ , Trigger :: Level ) ;
78+ gic. set_interrupt_priority ( PL031_IRQ , None , 0x80 ) ;
79+ gic. set_trigger ( PL031_IRQ , None , Trigger :: Level ) ;
8080 irq_enable ( ) ;
81- gic. enable_interrupt ( PL031_IRQ , true ) ;
81+ gic. enable_interrupt ( PL031_IRQ , None , true ) ;
8282
8383 // Wait for 3 seconds, without interrupts.
8484 let target = timestamp + 3 ;
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