pci_core: add infrastructure for devices to advertise pcie support with some basic functionality (microsoft#1930)

Adds the PCI_Express capability option for devices to advertise PCIe
support. This change will also us to add FLR support to the nvme_test
crate for further perf testing.

PciExpressCapability: New capability struct implementing PCI Express
Device Capabilities, Device Control, and Device Status registers

Spec digarams (From PCIe Base Spec 6.4) for reference:
<img width="1481" height="991" alt="image"
src="https://github.com/user-attachments/assets/a6f49e62-af03-4573-ab60-17637154aadc"
/>
<img width="1489" height="919" alt="image"
src="https://github.com/user-attachments/assets/21f6996c-eb8b-4fb6-b505-a113c37d9257"
/>

Being made as a helper PR to microsoft#1858 since that was getting a little too
large/complicated

---------

Co-authored-by: Copilot <[email protected]>
Co-authored-by: Matt LaFayette (Kurjanowicz) <[email protected]>

Author: 3 people

vm/devices/pci/pci_core/src/capabilities/pci_express.rs

@@ -48,7 +48,7 @@ impl PciExpressCapability {
     /// Creates a new PCI Express capability with FLR support.
     ///
     /// # Arguments
-    /// * `flr_handler` - Optional handler to be called when FLR is initiated. FLR support will be inferred if flr_handler = Some(_)
+    /// * `flr_handler` - Optional handler to be called when FLR is initiated. This emulator will report that FLR is supported if flr_handler = Some(_)
     pub fn new(flr_handler: Option<Arc<dyn FlrHandler>>) -> Self {
         Self {
             device_capabilities: pci_express::DeviceCapabilities::new()
@@ -65,8 +65,9 @@ impl PciExpressCapability {
         let old_flr = state.device_control.initiate_function_level_reset();
         let new_flr = new_control.initiate_function_level_reset();
 
-
-        // DEVNOTE: It is "safe" to drop a new FLR request if there is still a previous FLR request in progress. The PCIe spec indicates that such behavior is undefined, so we choose to ignore the new FLR request.
+        // DEVNOTE: It is "safe" to drop a new FLR request if there is still a previous
+        // FLR request in progress. The PCIe spec indicates that such behavior is undefined,
+        // so we choose to ignore the new FLR request.
         if new_flr && !old_flr {
             if let Some(handler) = &self.flr_handler {
                 handler.initiate_flr();
@@ -201,26 +202,20 @@ mod save_restore {
             pub device_control: u16,
             #[mesh(2)]
             pub device_status: u16,
+            #[mesh(3)]
+            pub flr_handler: u16,
         }
     }
 
     impl SaveRestore for PciExpressCapability {
         type SavedState = state::SavedState;
 
         fn save(&mut self) -> Result<Self::SavedState, SaveError> {
-            let state = self.state.lock();
-            Ok(state::SavedState {
-                device_control: state.device_control.into_bits(),
-                device_status: state.device_status.into_bits(),
-            })
+            Err(SaveError::NotSupported)
         }
 
-        fn restore(&mut self, saved_state: Self::SavedState) -> Result<(), RestoreError> {
-            let mut state = self.state.lock();
-            state.device_control =
-                pci_express::DeviceControl::from_bits(saved_state.device_control);
-            state.device_status = pci_express::DeviceStatus::from_bits(saved_state.device_status);
-            Ok(())
+        fn restore(&mut self, _: Self::SavedState) -> Result<(), RestoreError> {
+            Err(RestoreError::SavedStateNotSupported)
         }
     }
 }
@@ -297,7 +292,7 @@ mod tests {
 
         // Test Device Capabilities Register (offset 0x04) - FLR should not be set
         let device_caps_val = cap.read_u32(0x04);
-        assert_eq!(device_caps_val & PCI_EXPRESS_DEVICE_CAPS_FLR_BIT_MASK, 0); // FLR bit should not be set
+        assert_eq!(device_caps_val & PCI_EXPRESS_DEVICE_CAPS_FLR_BIT_MASK, 0);
     }
 
     #[test]

vm/devices/pci/pci_core/src/spec.rs

@@ -391,11 +391,11 @@ pub mod caps {
             ///
             /// Table pulled from PCI Express Base Specification Rev. 3.0
             ///
-            /// | Offset    | Bits 31-24       | Bits 23-16       | Bits 15-8        | Bits 7-0         |
-            /// |-----------|------------------|------------------|------------------|------------------|
-            /// | Cap + 0x0 | PCI Express Capabilities Register | Next Pointer     | Capability ID (0x10) |
+            /// | Offset    | Bits 31-24       | Bits 23-16       | Bits 15-8        | Bits 7-0             |
+            /// |-----------|------------------|----------------- |------------------|----------------------|
+            /// | Cap + 0x0 | PCI Express Capabilities Register   | Next Pointer     | Capability ID (0x10) |
             /// | Cap + 0x4 | Device Capabilities Register                                                  |
-            /// | Cap + 0x8 | Device Status    | Device Control                                            |
+            /// | Cap + 0x8 | Device Status    | Device Control                                             |
             pub enum PciExpressCapabilityHeader: u16 {
                 PCIE_CAPS       = 0x00,
                 DEVICE_CAPS     = 0x04,
@@ -419,7 +419,7 @@ pub mod caps {
             #[bits(3)]
             _reserved1: u32,
             pub role_based_error: bool,
-            pub err_cor_subclass_capabable: bool,
+            pub err_cor_subclass_capable: bool,
             pub rx_mps_fixed: bool,
             #[bits(8)]
             pub captured_slot_power_limit: u32,