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This repository was archived by the owner on Jul 6, 2019. It is now read-only.

Commit 7ade70a

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Merge pull request #196 from bgamari/misc
Miscellaneous warnings fixes
2 parents f1f1175 + b634656 commit 7ade70a

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5 files changed

+6
-3
lines changed

5 files changed

+6
-3
lines changed

src/zinc/drivers/chario.rs

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@@ -15,7 +15,6 @@
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//! Generic char output trait.
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use core::ops::Slice;
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use core::str::{Str, StrSlice};
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use core::slice::ImmutableSlice;
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use core::collections::Collection;

src/zinc/hal/cortex_m3/isr.rs

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@@ -46,9 +46,11 @@ pub extern fn isr_default_fault() {
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#[cfg(test)]
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pub extern fn isr_default_fault() { unimplemented!() }
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#[allow(non_upper_case_globals)]
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const ISRCount: uint = 16;
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#[link_section=".isr_vector"]
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#[allow(non_upper_case_globals)]
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#[no_mangle]
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pub static ISRVectors: [Option<unsafe extern fn()>, ..ISRCount] = [
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Some(__STACK_BASE),

src/zinc/hal/k20/isr.rs

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@@ -88,9 +88,11 @@ extern {
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fn isr_soft();
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}
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#[allow(non_upper_case_globals)]
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const ISRCount: uint = 95;
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#[link_section=".isr_vector_nvic"]
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#[allow(non_upper_case_globals)]
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#[no_mangle]
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pub static NVICVectors: [Option<unsafe extern fn()>, ..ISRCount] = [
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Some(isr_dma_0),

src/zinc/hal/k20/sim.rs

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@@ -18,7 +18,7 @@
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use super::pin;
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/// Enable clock to a PORTx peripheral
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#[allow(non_snake_case_functions)]
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#[allow(non_snake_case)]
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pub fn enable_PORT(port: pin::Port) {
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match port {
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pin::PortA => {reg::SIM.scgc5.set_porta(true);},

src/zinc/util/lang_items.rs

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@@ -33,6 +33,6 @@ extern fn begin_unwind() {}
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#[cfg(not(test))]
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#[lang="fail_fmt"]
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#[no_stack_check]
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pub fn fail_fmt(fmt: &Arguments, file_line: &(&'static str, uint)) -> ! {
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pub fn fail_fmt(_fmt: &Arguments, _file_line: &(&'static str, uint)) -> ! {
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loop { }
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}

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