@@ -82,19 +82,19 @@ uint32_t pclk_phase_default[2][VIDEO_SOURCE_NUM] = {
8282 },
8383 {
8484 // GOGGLE_VER_2
85- 0x00000001 ,
85+ 0x00000004 ,
8686 0x00000004 , // VIDEO_SOURCE_MENU_UI
87- 0x00000000 , // VIDEO_SOURCE_HDZERO_IN_720P60_50
88- 0x00000000 , // VIDEO_SOURCE_HDZERO_IN_720P90
89- 0x00000000 , // VIDEO_SOURCE_HDZERO_IN_1080P30
90- 0x00000000 , // VIDEO_SOURCE_AV_IN
91- 0x00000000 , // VIDEO_SOURCE_HDMI_IN_1080P50
92- 0x00000000 , // VIDEO_SOURCE_HDMI_IN_1080P60
93- 0x00000000 , // VIDEO_SOURCE_HDMI_IN_1080POTHER
94- 0x00000000 , // VIDEO_SOURCE_HDMI_IN_720P50
95- 0x00000000 , // VIDEO_SOURCE_HDMI_IN_720P60
96- 0x00000000 , // VIDEO_SOURCE_HDMI_IN_720P100
97- 0x00000000 , // VIDEO_SOURCE_TP2825_EX, DO NOT USE
87+ 0x00000004 , // VIDEO_SOURCE_HDZERO_IN_720P60_50
88+ 0x00000004 , // VIDEO_SOURCE_HDZERO_IN_720P90
89+ 0x00000004 , // VIDEO_SOURCE_HDZERO_IN_1080P30
90+ 0x00000004 , // VIDEO_SOURCE_AV_IN
91+ 0x00000004 , // VIDEO_SOURCE_HDMI_IN_1080P50
92+ 0x00000004 , // VIDEO_SOURCE_HDMI_IN_1080P60
93+ 0x00000004 , // VIDEO_SOURCE_HDMI_IN_1080POTHER
94+ 0x00000004 , // VIDEO_SOURCE_HDMI_IN_720P50
95+ 0x00000004 , // VIDEO_SOURCE_HDMI_IN_720P60
96+ 0x00000004 , // VIDEO_SOURCE_HDMI_IN_720P100
97+ 0x00000004 , // VIDEO_SOURCE_TP2825_EX, DO NOT USE
9898 },
9999};
100100
@@ -531,13 +531,21 @@ void csic_pclk_invert_set(uint8_t is_invert) {
531531void pclk_phase_set (video_source_t source ) {
532532 LOGI ("pclk_phase_set %d" , pclk_phase [source ]);
533533 // bit[0] hdmi in
534- IT66021_Set_Pclk ((pclk_phase [source ] >> 0 ) & 1 );
534+ if (source == VIDEO_SOURCE_HDMI_IN_1080P50 || source == VIDEO_SOURCE_HDMI_IN_1080P60 || source == VIDEO_SOURCE_HDMI_IN_1080POTHER ) {
535+ IT66021_Set_Pclk ((pclk_phase [source ] >> 0 ) & 1 , 1 );
536+ } else {
537+ IT66021_Set_Pclk ((pclk_phase [source ] >> 0 ) & 1 , 2 );
538+ }
535539
536540 // bit[1] analog in
537541 TP2825_Set_Pclk ((pclk_phase [source ] >> 1 ) & 1 );
538542
539543 // bit[2] osd
540- vdpo_sync_ctrl_set ((pclk_phase [source ] >> 2 ) & 1 , 0 , 0 );
544+ if (source == VIDEO_SOURCE_AV_IN ) {
545+ vdpo_sync_ctrl_set ((pclk_phase [source ] >> 2 ) & 1 , 1 , 0 );
546+ } else {
547+ vdpo_sync_ctrl_set ((pclk_phase [source ] >> 2 ) & 1 , 0 , 0 );
548+ }
541549
542550 // bit[3] dvr
543551 csic_pclk_invert_set ((pclk_phase [source ] >> 3 ) & 1 );
@@ -706,6 +714,37 @@ void Display_1080P30_t(int mode) {
706714 system_exec ("aww 0x06542018 0x00000044" ); // disable horizontal chroma FIR filter.
707715}
708716
717+ void Display_1080P24_t (int mode ) {
718+ OLED_display (0 );
719+ I2C_Write (ADDR_FPGA , 0x8C , 0x00 );
720+
721+ system_exec ("dispw -s vdpo 1080p60" );
722+ g_hw_stat .vdpo_tmg = VDPO_TMG_1080P60 ;
723+ vclk_phase_set (VIDEO_SOURCE_HDZERO_IN_1080P30 , 0 );
724+ pclk_phase_set (VIDEO_SOURCE_HDZERO_IN_1080P30 );
725+
726+ I2C_Write (ADDR_FPGA , 0x80 , 0x84 );
727+ // I2C_Write(ADDR_FPGA, 0x84, 0x00); // close OSD
728+
729+ DM5680_SetFPS (mode );
730+ MFPGA_Set1080P30 ();
731+
732+ if (GOGGLE_VER_2 == 0 )
733+ OLED_SetTMG (2 );
734+ else
735+ OLED_SetTMG (0 );
736+
737+ if (GOGGLE_VER_2 )
738+ I2C_Write (ADDR_FPGA , 0xa7 , 0x00 );
739+
740+ I2C_Write (ADDR_FPGA , 0x8C , 0x01 );
741+
742+ g_hw_stat .source_mode = SOURCE_MODE_HDZERO ;
743+ Display_VO_SWITCH (1 );
744+ OLED_display (1 );
745+ system_exec ("aww 0x06542018 0x00000044" ); // disable horizontal chroma FIR filter.
746+ }
747+
709748void Display_720P60_50 (int mode , uint8_t is_43 ) {
710749 pthread_mutex_lock (& hardware_mutex );
711750 Display_720P60_50_t (mode , is_43 );
@@ -718,6 +757,12 @@ void Display_720P90(int mode) {
718757 pthread_mutex_unlock (& hardware_mutex );
719758}
720759
760+ void Display_1080P24 (int mode ) {
761+ pthread_mutex_lock (& hardware_mutex );
762+ Display_1080P24_t (mode );
763+ pthread_mutex_unlock (& hardware_mutex );
764+ }
765+
721766void Display_1080P30 (int mode ) {
722767 pthread_mutex_lock (& hardware_mutex );
723768 Display_1080P30_t (mode );
@@ -777,16 +822,18 @@ int HDZERO_detect() // return = 1: vtmg to V536 changed
777822 break ;
778823 case VR_1080P30 :
779824 Display_1080P30_t (CAM_MODE );
780-
825+ break ;
826+ case VR_1080P24 :
827+ Display_1080P24_t (CAM_MODE );
781828 break ;
782829 default :
783830 LOGW ("cam_mode =%d not suppored!!\n " , CAM_MODE );
784831 break ;
785832 }
786833
787- if (CAM_MODE == VR_1080P30 )
834+ if (CAM_MODE == VR_1080P30 || CAM_MODE == VR_1080P24 )
788835 fhd_req = 1 ;
789- else if (cam_mode_last == VR_1080P30 )
836+ else if (cam_mode_last == VR_1080P30 || cam_mode_last == VR_1080P24 )
790837 fhd_req = -1 ;
791838 dvr_update_vi_conf (CAM_MODE );
792839 system_script (REC_STOP_LIVE );
@@ -820,6 +867,7 @@ void AV_Mode_Switch_fpga(int is_pal) {
820867 }
821868 I2C_Write (ADDR_FPGA , 0x06 , 0x0F );
822869 system_exec ("aww 0x06542018 0x00000044" ); // disable horizontal chroma FIR filter.
870+ vdpo_sync_ctrl_set ((pclk_phase [VIDEO_SOURCE_AV_IN ] >> 2 ) & 1 , 1 , 0 );
823871}
824872
825873void AV_Mode_Switch (int is_pal ) {
@@ -932,8 +980,9 @@ int AV_in_detect() // return = 1: vtmg to V536 changed
932980 g_hw_stat .av_pal_w = g_hw_stat .av_pal_w ? 0 : 1 ;
933981
934982 TP2825_Switch_Mode (g_hw_stat .av_pal_w );
935- if (GOGGLE_VER_2 )
983+ if (GOGGLE_VER_2 ) {
936984 AV_Mode_Switch (g_hw_stat .av_pal_w );
985+ }
937986 // LOGI("Switch mode:%d", g_hw_stat.av_pal_w);
938987
939988 if (g_hw_stat .av_pal_w )
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