Feature Request: Add Multiply-Accumulate (MAC) Unit Component

[Anish-Rooj-cpu]

Description

I'd like to propose adding a Multiply-Accumulate (MAC) unit to the arithmetic components library. This would be a valuable addition for users working on digital signal processing (DSP), filtering algorithms, and other applications requiring efficient multiply-accumulate operations.

Current Situation

Currently, Digital has excellent arithmetic components including:

• Adders (Add)
• Multipliers (Mul)
• Subtractors (Sub)
• Dividers (Div)
• Comparators (Comparator)

However, there's no dedicated MAC unit that combines multiplication and accumulation in a single component.

Proposed Component

A MAC unit that performs: accumulator = accumulator + (a × b)

Key Features

1. Inputs:

   • a, b: Operands (configurable bit width, n-bit)
   • clr: Clear/reset accumulator
   • en: Enable update (allows controlled accumulation)
   • Optional: init for preset value

2. Outputs:

   • mac: Accumulator value (configurable bit width, typically 2n-bit)
   • ovf: Overflow flag indicating when accumulator exceeds its capacity
   • Optional: ready flag for pipelined operation

3. Configuration Options:

   • Operand bit width (default: 8)
   • Accumulator bit width (default: operand width × 2)
   • Signed/unsigned mode selection
   • Saturation mode vs. wrap on overflow
   • Optional pipeline stages for high-frequency designs

Example Use Cases

1. Digital Filtering: Implementing FIR/IIR filters

   for each sample:
     accumulator = 0
     for each coefficient:
       accumulator = accumulator + (sample * coefficient)
   

2. Matrix Multiplication: Computing dot products

3. Signal Processing: Autocorrelation, convolution

4. Neural Networks: Weighted sum calculations

Benefits

• Reduced Circuit Complexity: One component instead of multiple adders, multipliers, and registers
• Better Performance: Internal architecture can be optimized for accumulation
• Improved Readability: Makes circuit diagrams cleaner for DSP applications
• HDL Generation: Can generate optimized VHDL/Verilog for MAC operations
• Consistency: Follows the pattern of existing arithmetic components

Implementation Approach

The implementation would follow the same pattern as existing components:

public class Mac extends Node implements Element, Countable {
    // Similar structure to Add.java and Mul.java
    // Uses observable pattern for reactive updates
    // Supports HDL generation
}

Alternative Approaches Considered

1. Manual Construction: Users can currently build MAC from separate Mul + Add + register

   • Drawback: More complex, harder to optimize, less readable
   • Why not preferred: DSP applications often require many MAC units

2. Parameterized Macro: Could use subcircuits

   • Drawback: Not as flexible or efficient

Additional Considerations

1. Backward Compatibility: New component won't affect existing circuits
2. Performance: Could be optimized more than separate components
3. Testing: Can be thoroughly tested with existing test framework
4. Documentation: Would need to add to component documentation

Questions for Discussion

1. Should the accumulator bit width be fixed at 2× operand width or configurable?
2. Should we support signed/unsigned modes?
3. Is saturation on overflow needed, or should it just wrap?
4. Should we include a "preset" input for initial accumulator value?
5. Any concerns about VHDL/Verilog generation complexity?

Additional Context

• Existing similar components: Add, Mul, Sub, Div
• Related DSP components that could be added in future: FIR filter, CORDIC
• Would be useful for users working on digital signal processing projects

I'm willing to implement this component and submit a pull request with:

• Complete Java implementation
• Unit tests
• Documentation updates
• Example circuits demonstrating usage

Looking forward to feedback and suggestions!