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2 parents f46f0e9 + da39e07 commit aff5048Copy full SHA for aff5048
drivers/gpu/drm/xe/xe_pci.c
@@ -436,6 +436,7 @@ static const struct pci_device_id pciidlist[] = {
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INTEL_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
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INTEL_ARL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
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INTEL_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
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+ INTEL_PVC_IDS(INTEL_VGA_DEVICE, &pvc_desc),
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INTEL_MTL_IDS(INTEL_VGA_DEVICE, &mtl_desc),
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INTEL_LNL_IDS(INTEL_VGA_DEVICE, &lnl_desc),
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INTEL_BMG_IDS(INTEL_VGA_DEVICE, &bmg_desc),
drivers/gpu/drm/xe/xe_pm.c
@@ -357,10 +357,6 @@ ALLOW_ERROR_INJECTION(xe_pm_init_early, ERRNO); /* See xe_pci_probe() */
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static u32 vram_threshold_value(struct xe_device *xe)
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{
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- /* FIXME: D3Cold temporarily disabled by default on BMG */
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- if (xe->info.platform == XE_BATTLEMAGE)
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- return 0;
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-
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return DEFAULT_VRAM_THRESHOLD;
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}
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drivers/gpu/drm/xe/xe_uc_fw.c
@@ -115,10 +115,13 @@ struct fw_blobs_by_type {
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#define XE_GT_TYPE_ANY XE_GT_TYPE_UNINITIALIZED
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#define XE_GUC_FIRMWARE_DEFS(fw_def, mmp_ver, major_ver) \
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+ fw_def(CRESCENTISLAND, GT_TYPE_ANY, mmp_ver(xe, guc, cri, 70, 49, 4)) \
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+ fw_def(NOVALAKE_S, GT_TYPE_ANY, mmp_ver(xe, guc, nvl, 70, 49, 4)) \
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fw_def(PANTHERLAKE, GT_TYPE_ANY, major_ver(xe, guc, ptl, 70, 49, 4)) \
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fw_def(BATTLEMAGE, GT_TYPE_ANY, major_ver(xe, guc, bmg, 70, 49, 4)) \
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fw_def(LUNARLAKE, GT_TYPE_ANY, major_ver(xe, guc, lnl, 70, 45, 2)) \
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fw_def(METEORLAKE, GT_TYPE_ANY, major_ver(i915, guc, mtl, 70, 44, 1)) \
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+ fw_def(PVC, GT_TYPE_ANY, mmp_ver(xe, guc, pvc, 70, 44, 1)) \
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fw_def(DG2, GT_TYPE_ANY, major_ver(i915, guc, dg2, 70, 45, 2)) \
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fw_def(DG1, GT_TYPE_ANY, major_ver(i915, guc, dg1, 70, 44, 1)) \
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fw_def(ALDERLAKE_N, GT_TYPE_ANY, major_ver(i915, guc, tgl, 70, 44, 1)) \
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