pm: handle reset prep IRQ

In the SoC warm reboot process, sometimes there are
instances where the ISH firmware fails to receive the
warm reboot request from PMC, leading to the failure to reboot
ISH firmware hence causing ISHTP kernel driver communication
failure with ISH firmware. This issue is observred when
there is an IPC request pending at the ISH and at the time
a warm reboot is initiated causing IPM driver timeout.

The IPM driver timeout is set to 1sec waiting for the Peer ACK.
Due to warm reboot, Peer ACK is not received leading to timeout
of 1sec. During this time ISH HW triggeres the RESET
PREP IRQ, but we do not observe ISR routine exexuted at firmware
side which is expected to handle the warm reboot.

Changes done to perform ish pm init using zephyr SYS_INIT() in
PRE_KERNEL_2 stage. This change helps handle the IRQ rightly and
invokes the ISR routine to handle the firmware reset.

Change-Id: I454bd75257cdfc1c8f37e582231f6fe7f5e8f91d

Author: Deshatty, Deepti

bsp_sedi/soc/intel_ish/pm/ish_pm.c

@@ -11,6 +11,7 @@
 #include "sedi_driver_uart.h"
 #include <sedi_driver_rtc.h>
 #include <zephyr/sys/printk.h>
+#include <zephyr/init.h>
 #include <zephyr/irq.h>
 #include <zephyr/drivers/interrupt_controller/ioapic.h>
 #include <zephyr/arch/x86/ia32/segmentation.h>
@@ -610,6 +611,16 @@ static void reset_prep_isr(void)
 
 void sedi_pm_init(void)
 {
+	/*TODO: remove the api */
+}
+
+static int ish_sedi_pm_init(void)
+{
+	/* register ISR */
+	IRQ_CONNECT(SEDI_IRQ_RESET_PREP, 4, reset_prep_isr, 0, IOAPIC_LEVEL);
+	IRQ_CONNECT(SEDI_IRQ_PMU2IOAPIC, 4, pmu_wakeup_isr, 0, IOAPIC_LEVEL);
+	IRQ_CONNECT(SEDI_IRQ_PCIEDEV, 2, pcie_dev_isr, 0, IOAPIC_LEVEL);
+
 	/* clear reset bit */
 	write32(ISH_RST_REG, 0);
 
@@ -631,10 +642,6 @@ void sedi_pm_init(void)
 	write32(PMU_ISH_FABRIC_CNT, (read32(PMU_ISH_FABRIC_CNT) & 0xffff0000) | FABRIC_IDLE_COUNT);
 	write32(PMU_PGCB_CLKGATE_CTRL, TRUNK_CLKGATE_COUNT);
 
-	IRQ_CONNECT(SEDI_IRQ_RESET_PREP, 5, reset_prep_isr, 0, IOAPIC_LEVEL);
-	IRQ_CONNECT(SEDI_IRQ_PMU2IOAPIC, 5, pmu_wakeup_isr, 0, IOAPIC_LEVEL);
-	IRQ_CONNECT(SEDI_IRQ_PCIEDEV, 5, pcie_dev_isr, 0, IOAPIC_LEVEL);
-
 	/* unmask reset prep avail interrupt */
 	write32(PMU_RST_PREP, 0);
 	sedi_core_irq_enable(SEDI_IRQ_RESET_PREP);
@@ -647,7 +654,10 @@ void sedi_pm_init(void)
 		write32(PMU_D3_STATUS, read32(PMU_D3_STATUS));
 
 	sedi_core_irq_enable(SEDI_IRQ_PCIEDEV);
+
+	return 0;
 }
+SYS_INIT(ish_sedi_pm_init, PRE_KERNEL_2, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
 
 void ish_pm_reset(enum ish_pm_state pm_state)
 {