This project implements a simple 8-bit RISC processor using Verilog HDL. It demonstrates fundamental CPU architecture concepts including datapath and control unit design.
- 8-bit ALU (ADD, SUB, AND, OR, XOR)
- 8×8 Register File
- Program Counter (PC)
- Instruction Memory (ROM)
- Control Unit (FSM: Fetch → Decode → Execute)
- Fully synthesizable design
- Simulated using Xilinx Vivado
| Bits | Field |
|---|---|
| [7:5] | Opcode |
| [4:3] | Destination Register |
| [2:0] | Source Register |
- ALU
- Register File
- Program Counter
- Instruction Memory
- Control Unit
- CPU Top Module
- Testbench verifies instruction execution
- Waveforms observed using Vivado simulator
- Add design file to Design Sources
- Add testbench to Simulation Sources
- Set testbench as top
- Run Behavioral Simulation
- Branch instructions
- Immediate operations
- Pipeline implementation
- Hazard detection
Jay Jain | Dhruvi Chavda