Commit 2425ecd
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Implement "real" AVX2 intrinsics and clean up x86 codegen (#115)
Resolves #114.
This may be best reviewed one commit at a time; one of them moves a lot
of stuff around.
This PR updates the x86 codegen to use actual AVX2 intrinsics (the ones
starting with `_mm256`). This is mostly straightforward, but there are a
few operations that require special attention. I've included some other
x86 codegen fixes and improvements that are somewhat interwoven:
- I've added tests for several operations that were previously untested.
Mainly these are 256-bit zip/unzip, widen/narrow, split/combine, and
integer equality comparisons. Note that these test cases were generated
by Claude.
- The x86 codegen now actually generates the correct code for integer
equality comparisons. Previously, it incorrectly generated "greater
than" comparisons instead.
- It also now uses the `blendv` family for "select" operations. Intel's
manual says these are available starting in SSE4.1. Not sure if there's
a reason this wasn't done before.
- For SSE4.2-level unzip operations, I've changed the codegen.
Previously, for `unzip_low`, it would shuffle the inputs to put the
even-indexed elements in both the lower and upper halves of the values,
then use `unpacklo` to select just the lower halves. Likewise, for
`unzip_high`, it would shuffle the inputs to put the *odd*-indexed
elements in both halves, and use `unpacklo` once more.
I've changed this so that `unzip_low` and `unzip_high` both use a
shuffle operation that moves the even-indexed elements into the lower
halves and the odd-indexed elements into the upper halves. `unzip_low`
uses `unpacklo` to select the lower halves, and `unzip_high` uses
`unpackhi` to select the upper halves. This means that if the user calls
both `unzip_low` and `unzip_high`, the shuffle operation's result can be
shared.
- I've implemented 8-bit multiplication based on [this StackOverflow
answer](https://stackoverflow.com/questions/8193601/sse-multiplication-16-x-uint8-t).
On the AVX2 side, most existing 128-bit operations have a
straightforward 256-bit counterpart, but some are more involved:
- The zip/unzip operations are a bit more complicated, since most AVX2
swizzle operations operate *within* each 128-bit lane. For 32-bit and
larger operations, there are special "lane-crossing" shuffles we can use
instead. Operations on smaller scalars require a combination of
intra-lane and "lane-crossing" shuffles.
- Splitting a 256-bit vector to a 128-bit one, or combining two 128-bit
vectors into a 256-bit one, can be done directly with AVX2 intrinsics.
- Widen/narrow operations can be done a bit more efficiently in AVX2.
Widening a u8x16 to a 16x16 can be done with a single
`_mm256_cvtepu8_epi16`. Narrowing a u16x16 to a u8x16 can done with two
shuffles: one to extract the lower bits of each 16-bit value within each
128-bit lane, and one to combine the two lanes.
I've consolidated much of the x86 codegen from `x86_common.rs`,
`arch/avx2.rs`, `arch/sse4_2.rs`, and `arch/x86_common.rs` into a single
`arch/x86.rs` file. I did this in the middle of some other commits;
sorry! The main AVX2 codegen was implemented before the reorganization,
but the split/combine and widen/narrow ops were implemented afterwards.
In the future, I'd like to rework and tidy up the codegen a bit more.
For instance, we're passing in things like vector types' widths
alongside those very same vector types, which is redundant. The `Arch`
trait is also very much not pulling its weight.1 parent deab67c commit 2425ecd
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- fearless_simd_tests/tests/harness
- fearless_simd/src/generated
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