diff --git a/hw/ip/csrng/data/csrng.hjson b/hw/ip/csrng/data/csrng.hjson index e31388f58c9d8..0a03c51c8dd23 100644 --- a/hw/ip/csrng/data/csrng.hjson +++ b/hw/ip/csrng/data/csrng.hjson @@ -20,10 +20,10 @@ dv_doc: "../doc/dv", hw_checklist: "../doc/checklist", sw_checklist: "/sw/device/lib/dif/dif_csrng", - version: "2.0.0", + version: "3.0.0", life_stage: "L1", - design_stage: "D2S", - verification_stage: "V2S", + design_stage: "D1", + verification_stage: "V1", dif_stage: "S2", clocking: [{clock: "clk_i", reset: "rst_ni"}], bus_interfaces: [ @@ -728,15 +728,6 @@ This bit will stay set until the next reset. ''' } - { bits: "2", - name: "SFIFO_CMDREQ_ERR", - desc: ''' - This bit will be set to one when an error has been detected for the - cmdreq FIFO. The type of error is reflected in the type status - bits (bits 28 through 30 of this register). - This bit will stay set until the next reset. - ''' - } { bits: "3", name: "SFIFO_RCSTAGE_ERR", desc: ''' @@ -755,24 +746,6 @@ This bit will stay set until the next reset. ''' } - { bits: "5", - name: "SFIFO_UPDREQ_ERR", - desc: ''' - This bit will be set to one when an error has been detected for the - updreq FIFO. The type of error is reflected in the type status - bits (bits 28 through 30 of this register). - This bit will stay set until the next reset. - ''' - } - { bits: "6", - name: "SFIFO_BENCREQ_ERR", - desc: ''' - This bit will be set to one when an error has been detected for the - bencreq FIFO. The type of error is reflected in the type status - bits (bits 28 through 30 of this register). - This bit will stay set until the next reset. - ''' - } { bits: "7", name: "SFIFO_BENCACK_ERR", desc: ''' @@ -782,15 +755,6 @@ This bit will stay set until the next reset. ''' } - { bits: "8", - name: "SFIFO_PDATA_ERR", - desc: ''' - This bit will be set to one when an error has been detected for the - pdata FIFO. The type of error is reflected in the type status - bits (bits 28 through 30 of this register). - This bit will stay set until the next reset. - ''' - } { bits: "9", name: "SFIFO_FINAL_ERR", desc: ''' @@ -975,12 +939,12 @@ swaccess: "ro", hwaccess: "hwo", fields: [ - { bits: "7:0", + { bits: "5:0", name: "MAIN_SM_STATE", desc: '''This is the state of the CSRNG main state machine. See the RTL file `csrng_main_sm` for the meaning of the values. ''' - resval: 0x4e + resval: 0x37 } ] }, diff --git a/hw/ip/csrng/doc/registers.md b/hw/ip/csrng/doc/registers.md index d0178063db56f..7446bf242e5e3 100644 --- a/hw/ip/csrng/doc/registers.md +++ b/hw/ip/csrng/doc/registers.md @@ -555,12 +555,12 @@ Writing a zero resets this status bit. Hardware detection of error conditions status register - Offset: `0x54` - Reset default: `0x0` -- Reset mask: `0x77f0ffff` +- Reset mask: `0x77f0fe9b` ### Fields ```wavejson -{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_UPDREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_PDATA_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} +{"reg": [{"name": "SFIFO_CMD_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_RCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_KEYVRC_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 2}, {"name": "SFIFO_BENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "SFIFO_FINAL_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GBENCACK_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GRCSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENREQ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GADSTAGE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_GGENBITS_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "SFIFO_CMDID_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 4}, {"name": "CMD_STAGE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "MAIN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_GEN_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDBE_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "DRBG_UPDOB_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "AES_CIPHER_SM_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "CMD_GEN_CNT_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}, {"name": "FIFO_WRITE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_READ_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"name": "FIFO_STATE_ERR", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 1}], "config": {"lanes": 1, "fontsize": 10, "vspace": 200}} ``` | Bits | Type | Reset | Name | @@ -585,13 +585,12 @@ Hardware detection of error conditions status register | 11 | ro | 0x0 | [SFIFO_GRCSTAGE_ERR](#err_code--sfifo_grcstage_err) | | 10 | ro | 0x0 | [SFIFO_GBENCACK_ERR](#err_code--sfifo_gbencack_err) | | 9 | ro | 0x0 | [SFIFO_FINAL_ERR](#err_code--sfifo_final_err) | -| 8 | ro | 0x0 | [SFIFO_PDATA_ERR](#err_code--sfifo_pdata_err) | +| 8 | | | Reserved | | 7 | ro | 0x0 | [SFIFO_BENCACK_ERR](#err_code--sfifo_bencack_err) | -| 6 | ro | 0x0 | [SFIFO_BENCREQ_ERR](#err_code--sfifo_bencreq_err) | -| 5 | ro | 0x0 | [SFIFO_UPDREQ_ERR](#err_code--sfifo_updreq_err) | +| 6:5 | | | Reserved | | 4 | ro | 0x0 | [SFIFO_KEYVRC_ERR](#err_code--sfifo_keyvrc_err) | | 3 | ro | 0x0 | [SFIFO_RCSTAGE_ERR](#err_code--sfifo_rcstage_err) | -| 2 | ro | 0x0 | [SFIFO_CMDREQ_ERR](#err_code--sfifo_cmdreq_err) | +| 2 | | | Reserved | | 1 | ro | 0x0 | [SFIFO_GENBITS_ERR](#err_code--sfifo_genbits_err) | | 0 | ro | 0x0 | [SFIFO_CMD_ERR](#err_code--sfifo_cmd_err) | @@ -698,30 +697,12 @@ final FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. -### ERR_CODE . SFIFO_PDATA_ERR -This bit will be set to one when an error has been detected for the -pdata FIFO. The type of error is reflected in the type status -bits (bits 28 through 30 of this register). -This bit will stay set until the next reset. - ### ERR_CODE . SFIFO_BENCACK_ERR This bit will be set to one when an error has been detected for the bencack FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. -### ERR_CODE . SFIFO_BENCREQ_ERR -This bit will be set to one when an error has been detected for the -bencreq FIFO. The type of error is reflected in the type status -bits (bits 28 through 30 of this register). -This bit will stay set until the next reset. - -### ERR_CODE . SFIFO_UPDREQ_ERR -This bit will be set to one when an error has been detected for the -updreq FIFO. The type of error is reflected in the type status -bits (bits 28 through 30 of this register). -This bit will stay set until the next reset. - ### ERR_CODE . SFIFO_KEYVRC_ERR This bit will be set to one when an error has been detected for the keyvrc FIFO. The type of error is reflected in the type status @@ -734,12 +715,6 @@ rcstage FIFO. The type of error is reflected in the type status bits (bits 28 through 30 of this register). This bit will stay set until the next reset. -### ERR_CODE . SFIFO_CMDREQ_ERR -This bit will be set to one when an error has been detected for the -cmdreq FIFO. The type of error is reflected in the type status -bits (bits 28 through 30 of this register). -This bit will stay set until the next reset. - ### ERR_CODE . SFIFO_GENBITS_ERR This bit will be set to one when an error has been detected for the command stage genbits FIFO. The type of error is reflected in the type status @@ -781,19 +756,19 @@ an interrupt or an alert. ## MAIN_SM_STATE Main state machine state debug register - Offset: `0x5c` -- Reset default: `0x4e` -- Reset mask: `0xff` +- Reset default: `0x37` +- Reset mask: `0x3f` ### Fields ```wavejson -{"reg": [{"name": "MAIN_SM_STATE", "bits": 8, "attr": ["ro"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +{"reg": [{"name": "MAIN_SM_STATE", "bits": 6, "attr": ["ro"], "rotate": -90}, {"bits": 26}], "config": {"lanes": 1, "fontsize": 10, "vspace": 150}} ``` | Bits | Type | Reset | Name | Description | |:------:|:------:|:-------:|:--------------|:-------------------------------------------------------------------------------------------------------------------| -| 31:8 | | | | Reserved | -| 7:0 | ro | 0x4e | MAIN_SM_STATE | This is the state of the CSRNG main state machine. See the RTL file `csrng_main_sm` for the meaning of the values. | +| 31:6 | | | | Reserved | +| 5:0 | ro | 0x37 | MAIN_SM_STATE | This is the state of the CSRNG main state machine. See the RTL file `csrng_main_sm` for the meaning of the values. | diff --git a/hw/ip/csrng/dv/env/csrng_env_pkg.sv b/hw/ip/csrng/dv/env/csrng_env_pkg.sv index 003011cf2bfc5..7fbfb7319c470 100644 --- a/hw/ip/csrng/dv/env/csrng_env_pkg.sv +++ b/hw/ip/csrng/dv/env/csrng_env_pkg.sv @@ -56,13 +56,9 @@ package csrng_env_pkg; typedef enum int { sfifo_cmd_error = 0, sfifo_genbits_error = 1, - sfifo_cmdreq_error = 2, sfifo_rcstage_error = 3, sfifo_keyvrc_error = 4, - sfifo_updreq_error = 5, - sfifo_bencreq_error = 6, sfifo_bencack_error = 7, - sfifo_pdata_error = 8, sfifo_final_error = 9, sfifo_gbencack_error = 10, sfifo_grcstage_error = 11, @@ -86,13 +82,9 @@ package csrng_env_pkg; // ERR_CODE sfifo_cmd_err = 0, sfifo_genbits_err = 1, - sfifo_cmdreq_err = 2, sfifo_rcstage_err = 3, sfifo_keyvrc_err = 4, - sfifo_updreq_err = 5, - sfifo_bencreq_err = 6, sfifo_bencack_err = 7, - sfifo_pdata_err = 8, sfifo_final_err = 9, sfifo_gbencack_err = 10, sfifo_grcstage_err = 11, @@ -113,13 +105,9 @@ package csrng_env_pkg; // ERR_CODE_TEST sfifo_cmd_err_test = 26, sfifo_genbits_err_test = 27, - sfifo_cmdreq_err_test = 28, sfifo_rcstage_err_test = 29, sfifo_keyvrc_err_test = 30, - sfifo_updreq_err_test = 31, - sfifo_bencreq_err_test = 32, sfifo_bencack_err_test = 33, - sfifo_pdata_err_test = 34, sfifo_final_err_test = 35, sfifo_gbencack_err_test = 36, sfifo_grcstage_err_test = 37, @@ -142,13 +130,9 @@ package csrng_env_pkg; typedef enum int { SFIFO_CMD_ERR = 0, SFIFO_GENBITS_ERR = 1, - SFIFO_CMDREQ_ERR = 2, SFIFO_RCSTAGE_ERR = 3, SFIFO_KEYVRC_ERR = 4, - SFIFO_UPDREQ_ERR = 5, - SFIFO_BENCREQ_ERR = 6, SFIFO_BENCACK_ERR = 7, - SFIFO_PDATA_ERR = 8, SFIFO_FINAL_ERR = 9, SFIFO_GBENCACK_ERR = 10, SFIFO_GRCSTAGE_ERR = 11, @@ -187,13 +171,9 @@ package csrng_env_pkg; sfifo_grcstage = 4, sfifo_gbencack = 5, sfifo_final = 6, - sfifo_pdata = 7, sfifo_bencack = 8, - sfifo_bencreq = 9, - sfifo_updreq = 10, sfifo_keyvrc = 11, sfifo_rcstage = 12, - sfifo_cmdreq = 13, sfifo_genbits = 14, sfifo_cmd = 15 } which_fifo_e; diff --git a/hw/ip/csrng/dv/env/csrng_path_if.sv b/hw/ip/csrng/dv/env/csrng_path_if.sv index b400d30c1cfad..05d8a18aab637 100644 --- a/hw/ip/csrng/dv/env/csrng_path_if.sv +++ b/hw/ip/csrng/dv/env/csrng_path_if.sv @@ -17,15 +17,15 @@ interface csrng_path_if case (fifo_name) inside "sfifo_cmd", "sfifo_genbits": return {core_path, $sformatf(".gen_cmd_stage[%0d]", app), ".u_csrng_cmd_stage.", fifo_name, "_", which_path}; - "sfifo_cmdreq", "sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.", + "sfifo_rcstage", "sfifo_keyvrc": return {core_path, ".u_csrng_ctr_drbg_cmd.", fifo_name, "_", which_path}; - "sfifo_updreq", "sfifo_bencreq", "sfifo_bencack", "sfifo_pdata", "sfifo_final": return + "sfifo_bencack", "sfifo_final": return {core_path, ".u_csrng_ctr_drbg_upd.", fifo_name, "_", which_path}; "sfifo_gbencack", "sfifo_grcstage", "sfifo_ggenreq", "sfifo_gadstage", "sfifo_ggenbits": return {core_path,".u_csrng_ctr_drbg_gen.sfifo_", fifo_name.substr(7, fifo_name.len()-1), "_", which_path}; "sfifo_cmdid": return {core_path, ".u_csrng_block_encrypt.", fifo_name, "_", which_path}; - default: `uvm_fatal("csrng_path_if", "Invalid fifo name!") + default: `uvm_fatal("csrng_path_if", $sformatf("%s: Invalid fifo name!", fifo_name)) endcase // case (fifo_name.substr(6, fifo_name.len()-1)) endfunction // fifo_err_path diff --git a/hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv b/hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv index f91f3bc2ba541..7f8acdbeb4e20 100644 --- a/hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv +++ b/hw/ip/csrng/dv/env/seq_lib/csrng_err_vseq.sv @@ -99,10 +99,10 @@ class csrng_err_vseq extends csrng_base_vseq; cfg.which_app_err_alert, fld_name), UVM_MEDIUM) case (cfg.which_err_code) inside - sfifo_cmd_err, sfifo_genbits_err, sfifo_cmdreq_err, sfifo_rcstage_err, sfifo_keyvrc_err, - sfifo_bencreq_err, sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err, - sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, sfifo_updreq_err, - sfifo_bencack_err, sfifo_pdata_err, sfifo_ggenreq_err: begin + sfifo_cmd_err, sfifo_genbits_err, sfifo_rcstage_err, sfifo_keyvrc_err, + sfifo_final_err, sfifo_gbencack_err, sfifo_grcstage_err, + sfifo_gadstage_err, sfifo_ggenbits_err, sfifo_cmdid_err, + sfifo_bencack_err, sfifo_ggenreq_err: begin fld = csr.get_field_by_name(fld_name); fifo_base_path = fld_name.substr(0, last_index-1); @@ -114,8 +114,8 @@ class csrng_err_vseq extends csrng_base_vseq; `uvm_info(`gfn, $sformatf("Forcing this FIFO error type %s", cfg.which_fifo_err.name()), UVM_MEDIUM) - if (cfg.which_err_code == sfifo_updreq_err || cfg.which_err_code == sfifo_bencack_err || - cfg.which_err_code == sfifo_pdata_err || cfg.which_err_code == sfifo_ggenreq_err) begin + if (cfg.which_err_code == sfifo_ggenreq_err || + cfg.which_err_code == sfifo_bencack_err) begin force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts, fld, 1'b1, cfg.which_fifo_err); @@ -221,17 +221,17 @@ class csrng_err_vseq extends csrng_base_vseq; cmd_gen_cnt_sel: begin fld = csr.get_field_by_name(fld_name); path = cfg.csrng_path_vif.cmd_gen_cnt_err_path(cfg.which_app_err_alert); - force_cnt_err(path, fld, 1'b1, 13); + force_cnt_err(path, fld, 1'b1, csrng_pkg::GenBitsCtrWidth); end drbg_upd_cnt_sel: begin fld = csr.get_field_by_name(fld_name); path = cfg.csrng_path_vif.drbg_upd_cnt_err_path(); - force_cnt_err(path, fld, 1'b1, 32); + force_cnt_err(path, fld, 1'b1, csrng_pkg::CtrLen); end drbg_gen_cnt_sel: begin fld = csr.get_field_by_name(fld_name); path = cfg.csrng_path_vif.drbg_gen_cnt_err_path(); - force_cnt_err(path, fld, 1'b1, 32); + force_cnt_err(path, fld, 1'b1, csrng_pkg::CtrLen); end endcase csr_rd(.ptr(ral.err_code), .value(backdoor_err_code_val)); @@ -263,9 +263,7 @@ class csrng_err_vseq extends csrng_base_vseq; value2 = fifo_err_value[1][path_key]; if (cfg.which_err_code == fifo_read_error && - ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_pdata) || - (cfg.which_fifo == sfifo_bencack) || (cfg.which_fifo == sfifo_updreq))) - begin + ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack))) begin force_fifo_err_exception(path1, path2, 1'b1, 1'b0, 1'b0, fld, 1'b1); // For sfifo_gadstage the down stream FIFO also takes inputs from sources other than @@ -303,9 +301,9 @@ class csrng_err_vseq extends csrng_base_vseq; csr_rd(.ptr(ral.err_code), .value(backdoor_err_code_val)); cov_vif.cg_err_code_sample(.err_code(backdoor_err_code_val)); end - sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_cmdreq_err_test, sfifo_rcstage_err_test, - sfifo_keyvrc_err_test, sfifo_updreq_err_test, sfifo_bencreq_err_test, sfifo_bencack_err_test, - sfifo_pdata_err_test, sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test, + sfifo_cmd_err_test, sfifo_genbits_err_test, sfifo_rcstage_err_test, + sfifo_keyvrc_err_test, sfifo_bencack_err_test, + sfifo_final_err_test, sfifo_gbencack_err_test, sfifo_grcstage_err_test, sfifo_ggenreq_err_test, sfifo_gadstage_err_test, sfifo_ggenbits_err_test, sfifo_cmdid_err_test, cmd_stage_sm_err_test, main_sm_err_test, drbg_gen_sm_err_test, drbg_updbe_sm_err_test, drbg_updob_sm_err_test, aes_cipher_sm_err_test, cmd_gen_cnt_err_test, diff --git a/hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv b/hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv index e184b0c233bbc..7cb4bdc90d9b2 100644 --- a/hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv +++ b/hw/ip/csrng/dv/env/seq_lib/csrng_intr_vseq.sv @@ -220,20 +220,17 @@ class csrng_intr_vseq extends csrng_base_vseq; last_index = find_index("_", fld_name, "last"); case (cfg.which_fatal_err) inside - sfifo_cmd_error, sfifo_genbits_error, sfifo_cmdreq_error, sfifo_rcstage_error, - sfifo_keyvrc_error, sfifo_bencreq_error, sfifo_final_error, sfifo_gbencack_error, + sfifo_cmd_error, sfifo_genbits_error, sfifo_rcstage_error, + sfifo_keyvrc_error, sfifo_final_error, sfifo_gbencack_error, sfifo_grcstage_error, sfifo_gadstage_error, sfifo_ggenbits_error, - sfifo_cmdid_error, sfifo_updreq_error, sfifo_bencack_error, sfifo_pdata_error, - sfifo_ggenreq_error: begin + sfifo_cmdid_error, sfifo_bencack_error, sfifo_ggenreq_error: begin fifo_base_path = fld_name.substr(0, last_index-1); foreach (path_exts[i]) begin fifo_forced_paths[i] = cfg.csrng_path_vif.fifo_err_path(cfg.NHwApps, fifo_base_path, path_exts[i]); end - if (cfg.which_fatal_err == sfifo_updreq_error || - cfg.which_fatal_err == sfifo_bencack_error || - cfg.which_fatal_err == sfifo_pdata_error || + if (cfg.which_fatal_err == sfifo_bencack_error || cfg.which_fatal_err == sfifo_ggenreq_error) begin force_all_fifo_errs_exception(fifo_forced_paths, fifo_forced_values, path_exts, ral.intr_state.cs_fatal_err, 1'b1, cfg.which_fifo_err); @@ -312,9 +309,7 @@ class csrng_intr_vseq extends csrng_base_vseq; value2 = fifo_err_value[1][path_key]; if (cfg.which_fatal_err == fifo_read_error && - ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_pdata) || - (cfg.which_fifo == sfifo_bencack) || (cfg.which_fifo == sfifo_updreq))) - begin + ((cfg.which_fifo == sfifo_ggenreq) || (cfg.which_fifo == sfifo_bencack))) begin force_fifo_err_exception(path1, path2, value1, value2, 1'b0, ral.intr_state.cs_fatal_err, 1'b1); end else begin diff --git a/hw/ip/csrng/rtl/csrng_cmd_stage.sv b/hw/ip/csrng/rtl/csrng_cmd_stage.sv index 9683eb11abd05..e060147367aeb 100644 --- a/hw/ip/csrng/rtl/csrng_cmd_stage.sv +++ b/hw/ip/csrng/rtl/csrng_cmd_stage.sv @@ -52,7 +52,6 @@ module csrng_cmd_stage import csrng_pkg::*; ( // Genbits parameters. localparam int GenBitsFifoWidth = 1 + BlkLen; localparam int GenBitsFifoDepth = 1; - localparam int GenBitsCntrWidth = 12; // Command FIFO. logic [CmdBusWidth-1:0] sfifo_cmd_rdata; @@ -84,7 +83,7 @@ module csrng_cmd_stage import csrng_pkg::*; ( logic cmd_gen_cnt_last; logic cmd_final_ack; logic cmd_err_ack; - logic [GenBitsCntrWidth-1:0] cmd_gen_cnt; + logic [GenBitsCtrWidth-1:0] cmd_gen_cnt; csrng_cmd_sts_e err_sts; logic reseed_cnt_exceeded; logic invalid_cmd_seq; @@ -193,17 +192,17 @@ module csrng_cmd_stage import csrng_pkg::*; ( // SEC_CM: GEN_CMD.CTR.REDUN prim_count #( - .Width(GenBitsCntrWidth), - .ResetValue({GenBitsCntrWidth{1'b1}}) + .Width(GenBitsCtrWidth), + .ResetValue({GenBitsCtrWidth{1'b1}}) ) u_prim_count_cmd_gen_cntr ( .clk_i, .rst_ni, .clr_i(!cs_enable_i), .set_i(cmd_gen_1st_req), - .set_cnt_i(sfifo_cmd_rdata[12+:GenBitsCntrWidth]), + .set_cnt_i(sfifo_cmd_rdata[12 +: GenBitsCtrWidth]), .incr_en_i(1'b0), .decr_en_i(cmd_gen_cnt_dec), // Count down. - .step_i(GenBitsCntrWidth'(1)), + .step_i(GenBitsCtrWidth'(1)), .commit_i(1'b1), .cnt_o(cmd_gen_cnt), .cnt_after_commit_o(), @@ -375,7 +374,7 @@ module csrng_cmd_stage import csrng_pkg::*; ( cmd_gen_1st_req = 1'b1; cmd_arb_sop_o = 1'b1; cmd_fifo_pop = 1'b1; - if (sfifo_cmd_rdata[12+:GenBitsCntrWidth] == GenBitsCntrWidth'(1)) begin + if (sfifo_cmd_rdata[12 +: GenBitsCtrWidth] == GenBitsCtrWidth'(1)) begin cmd_gen_cnt_last = 1'b1; end if (cmd_len == '0) begin @@ -443,7 +442,7 @@ module csrng_cmd_stage import csrng_pkg::*; ( cmd_gen_inc_req = 1'b1; state_d = GenCmdChk; // Check for final genbits beat. - if (cmd_gen_cnt == GenBitsCntrWidth'(1)) begin + if (cmd_gen_cnt == GenBitsCtrWidth'(1)) begin cmd_gen_cnt_last = 1'b1; end end diff --git a/hw/ip/csrng/rtl/csrng_core.sv b/hw/ip/csrng/rtl/csrng_core.sv index 4de0f2e0ff151..cf6fb2375140f 100644 --- a/hw/ip/csrng/rtl/csrng_core.sv +++ b/hw/ip/csrng/rtl/csrng_core.sv @@ -95,7 +95,7 @@ module csrng_core import csrng_pkg::*; #( csrng_state_t state_db_rd_data; logic [CmdBusWidth-1:0] acmd_bus; - logic [2:0] acmd_hold; + acmd_e acmd_hold; logic [SeedLen-1:0] packer_adata; logic [ADataDepthClog-1:0] packer_adata_depth; @@ -132,27 +132,15 @@ module csrng_core import csrng_pkg::*; #( logic [InstIdWidth-1:0] state_db_sts_id; logic acmd_accept; - logic instant_req; - logic reseed_req; - logic generate_req; - logic update_req; - logic uninstant_req; + logic main_sm_cmd_vld; logic clr_adata_packer; - logic ctr_drbg_cmd_sfifo_cmdreq_err_sum; - logic [2:0] ctr_drbg_cmd_sfifo_cmdreq_err; logic ctr_drbg_cmd_sfifo_rcstage_err_sum; logic [2:0] ctr_drbg_cmd_sfifo_rcstage_err; logic ctr_drbg_cmd_sfifo_keyvrc_err_sum; logic [2:0] ctr_drbg_cmd_sfifo_keyvrc_err; - logic ctr_drbg_upd_sfifo_updreq_err_sum; - logic [2:0] ctr_drbg_upd_sfifo_updreq_err; - logic ctr_drbg_upd_sfifo_bencreq_err_sum; - logic [2:0] ctr_drbg_upd_sfifo_bencreq_err; logic ctr_drbg_upd_sfifo_bencack_err_sum; logic [2:0] ctr_drbg_upd_sfifo_bencack_err; - logic ctr_drbg_upd_sfifo_pdata_err_sum; - logic [2:0] ctr_drbg_upd_sfifo_pdata_err; logic ctr_drbg_upd_sfifo_final_err_sum; logic [2:0] ctr_drbg_upd_sfifo_final_err; logic ctr_drbg_gen_sfifo_gbencack_err_sum; @@ -303,14 +291,13 @@ module csrng_core import csrng_pkg::*; #( prim_mubi_pkg::mubi4_t [Flag0Copies-1:0] mubi_flag0_fanout; // flops - logic [2:0] acmd_q, acmd_d; + acmd_e acmd_q, acmd_d; logic [3:0] shid_q, shid_d; logic gen_last_q, gen_last_d; mubi4_t flag0_q, flag0_d; logic [NumAppsLg-1:0] cmd_arb_idx_q, cmd_arb_idx_d; logic statedb_wr_select_q, statedb_wr_select_d; logic genbits_stage_fips_sw_q, genbits_stage_fips_sw_d; - logic cmd_req_dly_q, cmd_req_dly_d; logic [CmdWidth-1:0] cmd_req_ccmd_dly_q, cmd_req_ccmd_dly_d; logic cs_aes_halt_q, cs_aes_halt_d; logic [SeedLen-1:0] entropy_src_seed_q, entropy_src_seed_d; @@ -323,14 +310,13 @@ module csrng_core import csrng_pkg::*; #( always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - acmd_q <= '0; + acmd_q <= INV; shid_q <= '0; gen_last_q <= '0; flag0_q <= prim_mubi_pkg::MuBi4False; cmd_arb_idx_q <= '0; statedb_wr_select_q <= '0; genbits_stage_fips_sw_q <= '0; - cmd_req_dly_q <= '0; cmd_req_ccmd_dly_q <= '0; cs_aes_halt_q <= '0; entropy_src_seed_q <= '0; @@ -348,7 +334,6 @@ module csrng_core import csrng_pkg::*; #( cmd_arb_idx_q <= cmd_arb_idx_d; statedb_wr_select_q <= statedb_wr_select_d; genbits_stage_fips_sw_q <= genbits_stage_fips_sw_d; - cmd_req_dly_q <= cmd_req_dly_d; cmd_req_ccmd_dly_q <= cmd_req_ccmd_dly_d; cs_aes_halt_q <= cs_aes_halt_d; entropy_src_seed_q <= entropy_src_seed_d; @@ -443,13 +428,9 @@ module csrng_core import csrng_pkg::*; #( assign event_cs_fatal_err = (cs_enable_fo[1] && ( (|cmd_stage_sfifo_cmd_err_sum) || (|cmd_stage_sfifo_genbits_err_sum) || - ctr_drbg_cmd_sfifo_cmdreq_err_sum || ctr_drbg_cmd_sfifo_rcstage_err_sum || ctr_drbg_cmd_sfifo_keyvrc_err_sum || - ctr_drbg_upd_sfifo_updreq_err_sum || - ctr_drbg_upd_sfifo_bencreq_err_sum || ctr_drbg_upd_sfifo_bencack_err_sum || - ctr_drbg_upd_sfifo_pdata_err_sum || ctr_drbg_upd_sfifo_final_err_sum || ctr_drbg_gen_sfifo_gbencack_err_sum || ctr_drbg_gen_sfifo_grcstage_err_sum || @@ -465,20 +446,12 @@ module csrng_core import csrng_pkg::*; #( fatal_loc_events; // set fifo errors that are single instances of source - assign ctr_drbg_cmd_sfifo_cmdreq_err_sum = (|ctr_drbg_cmd_sfifo_cmdreq_err) || - err_code_test_bit[2]; assign ctr_drbg_cmd_sfifo_rcstage_err_sum = (|ctr_drbg_cmd_sfifo_rcstage_err) || err_code_test_bit[3]; assign ctr_drbg_cmd_sfifo_keyvrc_err_sum = (|ctr_drbg_cmd_sfifo_keyvrc_err) || err_code_test_bit[4]; - assign ctr_drbg_upd_sfifo_updreq_err_sum = (|ctr_drbg_upd_sfifo_updreq_err) || - err_code_test_bit[5]; - assign ctr_drbg_upd_sfifo_bencreq_err_sum = (|ctr_drbg_upd_sfifo_bencreq_err) || - err_code_test_bit[6]; assign ctr_drbg_upd_sfifo_bencack_err_sum = (|ctr_drbg_upd_sfifo_bencack_err) || err_code_test_bit[7]; - assign ctr_drbg_upd_sfifo_pdata_err_sum = (|ctr_drbg_upd_sfifo_pdata_err) || - err_code_test_bit[8]; assign ctr_drbg_upd_sfifo_final_err_sum = (|ctr_drbg_upd_sfifo_final_err) || err_code_test_bit[9]; assign ctr_drbg_gen_sfifo_gbencack_err_sum = (|ctr_drbg_gen_sfifo_gbencack_err) || @@ -515,13 +488,9 @@ module csrng_core import csrng_pkg::*; #( ctr_drbg_gen_sfifo_grcstage_err[2] || ctr_drbg_gen_sfifo_gbencack_err[2] || ctr_drbg_upd_sfifo_final_err[2] || - ctr_drbg_upd_sfifo_pdata_err[2] || ctr_drbg_upd_sfifo_bencack_err[2] || - ctr_drbg_upd_sfifo_bencreq_err[2] || - ctr_drbg_upd_sfifo_updreq_err[2] || ctr_drbg_cmd_sfifo_keyvrc_err[2] || ctr_drbg_cmd_sfifo_rcstage_err[2] || - ctr_drbg_cmd_sfifo_cmdreq_err[2] || (|cmd_stage_sfifo_genbits_err_wr) || (|cmd_stage_sfifo_cmd_err_wr) || err_code_test_bit[28]; @@ -533,13 +502,9 @@ module csrng_core import csrng_pkg::*; #( ctr_drbg_gen_sfifo_grcstage_err[1] || ctr_drbg_gen_sfifo_gbencack_err[1] || ctr_drbg_upd_sfifo_final_err[1] || - ctr_drbg_upd_sfifo_pdata_err[1] || ctr_drbg_upd_sfifo_bencack_err[1] || - ctr_drbg_upd_sfifo_bencreq_err[1] || - ctr_drbg_upd_sfifo_updreq_err[1] || ctr_drbg_cmd_sfifo_keyvrc_err[1] || ctr_drbg_cmd_sfifo_rcstage_err[1] || - ctr_drbg_cmd_sfifo_cmdreq_err[1] || (|cmd_stage_sfifo_genbits_err_rd) || (|cmd_stage_sfifo_cmd_err_rd) || err_code_test_bit[29]; @@ -551,13 +516,9 @@ module csrng_core import csrng_pkg::*; #( ctr_drbg_gen_sfifo_grcstage_err[0] || ctr_drbg_gen_sfifo_gbencack_err[0] || ctr_drbg_upd_sfifo_final_err[0] || - ctr_drbg_upd_sfifo_pdata_err[0] || ctr_drbg_upd_sfifo_bencack_err[0] || - ctr_drbg_upd_sfifo_bencreq_err[0] || - ctr_drbg_upd_sfifo_updreq_err[0] || ctr_drbg_cmd_sfifo_keyvrc_err[0] || ctr_drbg_cmd_sfifo_rcstage_err[0] || - ctr_drbg_cmd_sfifo_cmdreq_err[0] || (|cmd_stage_sfifo_genbits_err_st) || (|cmd_stage_sfifo_cmd_err_st) || err_code_test_bit[30]; @@ -571,10 +532,6 @@ module csrng_core import csrng_pkg::*; #( assign hw2reg.err_code.sfifo_genbits_err.de = cs_enable_fo[3] && (|cmd_stage_sfifo_genbits_err_sum); - assign hw2reg.err_code.sfifo_cmdreq_err.d = 1'b1; - assign hw2reg.err_code.sfifo_cmdreq_err.de = cs_enable_fo[4] && - ctr_drbg_cmd_sfifo_cmdreq_err_sum; - assign hw2reg.err_code.sfifo_rcstage_err.d = 1'b1; assign hw2reg.err_code.sfifo_rcstage_err.de = cs_enable_fo[5] && ctr_drbg_cmd_sfifo_rcstage_err_sum; @@ -583,22 +540,10 @@ module csrng_core import csrng_pkg::*; #( assign hw2reg.err_code.sfifo_keyvrc_err.de = cs_enable_fo[6] && ctr_drbg_cmd_sfifo_keyvrc_err_sum; - assign hw2reg.err_code.sfifo_updreq_err.d = 1'b1; - assign hw2reg.err_code.sfifo_updreq_err.de = cs_enable_fo[7] && - ctr_drbg_upd_sfifo_updreq_err_sum; - - assign hw2reg.err_code.sfifo_bencreq_err.d = 1'b1; - assign hw2reg.err_code.sfifo_bencreq_err.de = cs_enable_fo[8] && - ctr_drbg_upd_sfifo_bencreq_err_sum; - assign hw2reg.err_code.sfifo_bencack_err.d = 1'b1; assign hw2reg.err_code.sfifo_bencack_err.de = cs_enable_fo[9] && ctr_drbg_upd_sfifo_bencack_err_sum; - assign hw2reg.err_code.sfifo_pdata_err.d = 1'b1; - assign hw2reg.err_code.sfifo_pdata_err.de = cs_enable_fo[10] && - ctr_drbg_upd_sfifo_pdata_err_sum; - assign hw2reg.err_code.sfifo_final_err.d = 1'b1; assign hw2reg.err_code.sfifo_final_err.de = cs_enable_fo[11] && ctr_drbg_upd_sfifo_final_err_sum; @@ -1032,12 +977,12 @@ module csrng_core import csrng_pkg::*; #( assign hw2reg.recov_alert_sts.acmd_flag0_field_alert.d = acmd_flag0_pfa; // parse the command bus - assign acmd_hold = acmd_sop ? acmd_bus[2:0] : acmd_q; + assign acmd_hold = acmd_sop ? acmd_e'(acmd_bus[CmdWidth-1:0]) : acmd_q; // TODO(#28153) rewrite as an always_comb block assign acmd_d = - (!cs_enable_fo[32]) ? '0 : - acmd_sop ? acmd_bus[2:0] : + (!cs_enable_fo[32]) ? INV : + acmd_sop ? acmd_e'(acmd_bus[CmdWidth-1:0]) : acmd_q; assign shid_d = @@ -1084,15 +1029,11 @@ module csrng_core import csrng_pkg::*; #( .acmd_accept_o (acmd_accept), .acmd_i (acmd_hold), .acmd_eop_i (acmd_eop), - .ctr_drbg_cmd_req_rdy_i(ctr_drbg_cmd_req_rdy), .flag0_i (flag0_fo[0]), .cmd_entropy_req_o (cmd_entropy_req), .cmd_entropy_avail_i (cmd_entropy_avail), - .instant_req_o (instant_req), - .reseed_req_o (reseed_req), - .generate_req_o (generate_req), - .update_req_o (update_req), - .uninstant_req_o (uninstant_req), + .cmd_vld_o (main_sm_cmd_vld), + .cmd_rdy_i (ctr_drbg_cmd_req_rdy), .clr_adata_packer_o (clr_adata_packer), .cmd_complete_i (state_db_wr_vld), .local_escalate_i (fatal_loc_events), @@ -1229,8 +1170,7 @@ module csrng_core import csrng_pkg::*; #( cmd_entropy_req && cmd_entropy_avail ? entropy_src_hw_if_i.es_fips : entropy_src_fips_q; - assign cmd_entropy = entropy_src_seed_q; - + assign cmd_entropy = entropy_src_seed_q; assign cmd_entropy_fips = entropy_src_fips_q; //------------------------------------- @@ -1257,13 +1197,8 @@ module csrng_core import csrng_pkg::*; #( // inputs: 416b K,V,RC, 384b adata // outputs: 416b K,V,RC - assign cmd_req_dly_d = - (!cs_enable_fo[45]) ? '0 : - (instant_req || reseed_req || generate_req || update_req || uninstant_req); - - assign ctr_drbg_cmd_req_vld = cmd_req_dly_q; - - assign cmd_req_ccmd_dly_d = (!cs_enable_fo[44]) ? '0 : acmd_hold; + assign ctr_drbg_cmd_req_vld = !cs_enable_fo[45] ? 1'b0 : main_sm_cmd_vld; + assign cmd_req_ccmd_dly_d = !cs_enable_fo[44] ? '0 : acmd_hold; assign ctr_drbg_cmd_req_data = '{ inst_id: shid_q, @@ -1301,7 +1236,6 @@ module csrng_core import csrng_pkg::*; #( .update_rsp_rdy_o (cmd_upd_rsp_rdy), .update_rsp_data_i(upd_rsp_data), - .fifo_cmdreq_err_o (ctr_drbg_cmd_sfifo_cmdreq_err), .fifo_rcstage_err_o(ctr_drbg_cmd_sfifo_rcstage_err), .fifo_keyvrc_err_o (ctr_drbg_cmd_sfifo_keyvrc_err) ); @@ -1341,10 +1275,7 @@ module csrng_core import csrng_pkg::*; #( .block_encrypt_rsp_data_i(block_encrypt_rsp_data), .ctr_err_o (ctr_drbg_upd_v_ctr_err), - .fifo_updreq_err_o (ctr_drbg_upd_sfifo_updreq_err), - .fifo_bencreq_err_o (ctr_drbg_upd_sfifo_bencreq_err), .fifo_bencack_err_o (ctr_drbg_upd_sfifo_bencack_err), - .fifo_pdata_err_o (ctr_drbg_upd_sfifo_pdata_err), .fifo_final_err_o (ctr_drbg_upd_sfifo_final_err), .sm_block_enc_req_err_o(drbg_updbe_sm_err), .sm_block_enc_rsp_err_o(drbg_updob_sm_err) @@ -1355,16 +1286,18 @@ module csrng_core import csrng_pkg::*; #( // local helper signals csrng_upd_data_t upd_arb_din[2]; + logic [1:0] upd_arb_gnt; + prim_arbiter_ppc #( - .N (2), // (cmd req and gen req) + .N(2), // (cmd req and gen req) .DW(UpdDataWidth) ) u_prim_arbiter_ppc_updblk_arb ( .clk_i (clk_i), .rst_ni (rst_ni), .req_chk_i(cs_enable_fo[1]), .req_i ({gen_upd_req_vld, cmd_upd_req_vld}), - .gnt_o ({gen_upd_req_rdy, cmd_upd_req_rdy}), .data_i (upd_arb_din), + .gnt_o (upd_arb_gnt), .idx_o (), .valid_o (upd_arb_req_vld), .data_o (upd_arb_req_data), @@ -1374,6 +1307,9 @@ module csrng_core import csrng_pkg::*; #( assign upd_arb_din[0] = cmd_upd_req_data; assign upd_arb_din[1] = gen_upd_req_data; + assign cmd_upd_req_rdy = upd_arb_gnt[0]; + assign gen_upd_req_rdy = upd_arb_gnt[1]; + assign cmd_upd_rsp_vld = upd_rsp_vld && (upd_rsp_data.cmd != GENU); assign gen_upd_rsp_vld = upd_rsp_vld && (upd_rsp_data.cmd == GENU); @@ -1543,13 +1479,17 @@ module csrng_core import csrng_pkg::*; #( // unused signals logic unused_err_code_test_bit; + logic unused_enable_fo; logic unused_reg2hw_genbits; logic unused_int_state_val; logic unused_reseed_interval; logic [SeedLen-1:0] unused_gen_rsp_pdata; logic unused_state_db_inst_state; - assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[27:26]); + assign unused_err_code_test_bit = (|err_code_test_bit[19:16]) || (|err_code_test_bit[27:26]) || + err_code_test_bit[8] || (|err_code_test_bit[6:5]) || + err_code_test_bit[2]; + assign unused_enable_fo = cs_enable_fo[10] || (|cs_enable_fo[8:7]) || cs_enable_fo[4]; assign unused_reg2hw_genbits = (|reg2hw.genbits.q); assign unused_int_state_val = (|reg2hw.int_state_val.q); assign unused_reseed_interval = reg2hw.reseed_interval.qe; diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv index 5546c6b2644eb..5ab21ab4177fe 100644 --- a/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv +++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_cmd.sv @@ -41,19 +41,15 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; ( input csrng_upd_data_t update_rsp_data_i, // Error status outputs - output logic [2:0] fifo_cmdreq_err_o, output logic [2:0] fifo_rcstage_err_o, output logic [2:0] fifo_keyvrc_err_o ); - localparam int CmdreqFifoWidth = CoreDataWidth + SeedLen + 1; localparam int RCStageFifoWidth = CoreDataWidth + 1; localparam int KeyVRCFifoWidth = CoreDataWidth + 1; // signals - csrng_core_data_t cmdreq_data; - logic [SeedLen-1:0] cmdreq_entropy; - logic cmdreq_glast; + csrng_core_data_t req_data; csrng_core_data_t rcstage_data; logic rcstage_glast; @@ -62,19 +58,11 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; ( logic keyvrc_glast; logic [SeedLen-1:0] prep_seed_material; - logic [KeyLen-1:0] prep_key; - logic [BlkLen-1:0] prep_v; - logic [CtrLen-1:0] prep_rc; + logic [KeyLen-1:0] prep_key; + logic [BlkLen-1:0] prep_v; + logic [CtrLen-1:0] prep_rc; logic prep_gen_adata_null; - // cmdreq fifo - logic sfifo_cmdreq_wvld; - logic sfifo_cmdreq_wrdy; - logic [CmdreqFifoWidth-1:0] sfifo_cmdreq_wdata; - logic sfifo_cmdreq_rvld; - logic sfifo_cmdreq_rrdy; - logic [CmdreqFifoWidth-1:0] sfifo_cmdreq_rdata; - // rcstage fifo logic sfifo_rcstage_wvld; logic sfifo_rcstage_wrdy; @@ -102,99 +90,59 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; ( end end + //-------------------------------------------- - // input request fifo for staging cmd request + // Prepare/mux values for update step //-------------------------------------------- - csrng_core_data_t req_data_fifo; - - prim_fifo_sync #( - .Width(CmdreqFifoWidth), - .Pass(0), - .Depth(1), - .OutputZeroIfEmpty(1'b0) - ) u_prim_fifo_sync_cmdreq ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .clr_i (!enable_i), - .wvalid_i(sfifo_cmdreq_wvld), - .wready_o(sfifo_cmdreq_wrdy), - .wdata_i (sfifo_cmdreq_wdata), - .rvalid_o(sfifo_cmdreq_rvld), - .rready_i(sfifo_cmdreq_rrdy), - .rdata_o (sfifo_cmdreq_rdata), - .full_o (), - .depth_o (), - .err_o () - ); + assign req_rdy_o = enable_i && sfifo_rcstage_wrdy && (update_req_rdy_i || prep_gen_adata_null); always_comb begin - req_data_fifo = req_data_i; + req_data = req_data_i; // Insert the FIPS info from entropy source on instantiate and reseed commands. // Else, keep the existing info (from state db). - req_data_fifo.fips = ((req_data_i.cmd == INS) || (req_data_i.cmd == RES)) ? - req_entropy_fips_i : req_data_i.fips; + req_data.fips = ((req_data_i.cmd == INS) || (req_data_i.cmd == RES)) ? + req_entropy_fips_i : req_data_i.fips; end - assign sfifo_cmdreq_wdata = {req_glast_i, - req_entropy_i, - req_data_fifo}; - - assign {cmdreq_glast, - cmdreq_entropy, - cmdreq_data} = sfifo_cmdreq_rdata; - - assign sfifo_cmdreq_wvld = enable_i && req_vld_i; - assign sfifo_cmdreq_rrdy = enable_i && (update_req_rdy_i || gen_adata_null_q) && - sfifo_cmdreq_rvld; - assign req_rdy_o = sfifo_cmdreq_wrdy; - - assign fifo_cmdreq_err_o = - {( sfifo_cmdreq_wvld && !sfifo_cmdreq_wrdy), - ( sfifo_cmdreq_rrdy && !sfifo_cmdreq_rvld), - (!sfifo_cmdreq_wrdy && !sfifo_cmdreq_rvld)}; - - //-------------------------------------------- - // Prepare (mostly: mux) values for update step - //-------------------------------------------- - assign prep_seed_material = - (cmdreq_data.cmd == INS) ? (cmdreq_entropy ^ cmdreq_data.pdata) : - (cmdreq_data.cmd == RES) ? (cmdreq_entropy ^ cmdreq_data.pdata) : - (cmdreq_data.cmd == GEN) ? cmdreq_data.pdata : - (cmdreq_data.cmd == UPD) ? cmdreq_data.pdata : + (req_data.cmd == INS) ? (req_entropy_i ^ req_data.pdata) : + (req_data.cmd == RES) ? (req_entropy_i ^ req_data.pdata) : + (req_data.cmd == GEN) ? req_data.pdata : + (req_data.cmd == UPD) ? req_data.pdata : '0; assign prep_key = - (cmdreq_data.cmd == INS) ? '0 : - (cmdreq_data.cmd == RES) ? cmdreq_data.key : - (cmdreq_data.cmd == GEN) ? cmdreq_data.key : - (cmdreq_data.cmd == UPD) ? cmdreq_data.key : + (req_data.cmd == INS) ? '0 : + (req_data.cmd == RES) ? req_data.key : + (req_data.cmd == GEN) ? req_data.key : + (req_data.cmd == UPD) ? req_data.key : '0; assign prep_v = - (cmdreq_data.cmd == INS) ? '0 : - (cmdreq_data.cmd == RES) ? cmdreq_data.v : - (cmdreq_data.cmd == GEN) ? cmdreq_data.v : - (cmdreq_data.cmd == UPD) ? cmdreq_data.v : + (req_data.cmd == INS) ? '0 : + (req_data.cmd == RES) ? req_data.v : + (req_data.cmd == GEN) ? req_data.v : + (req_data.cmd == UPD) ? req_data.v : '0; assign prep_rc = - (cmdreq_data.cmd == INS) ? '0 : - (cmdreq_data.cmd == RES) ? '0 : - (cmdreq_data.cmd == GEN) ? cmdreq_data.rs_ctr : - (cmdreq_data.cmd == UPD) ? cmdreq_data.rs_ctr : + (req_data.cmd == INS) ? '0 : + (req_data.cmd == RES) ? '0 : + (req_data.cmd == GEN) ? req_data.rs_ctr : + (req_data.cmd == UPD) ? req_data.rs_ctr : '0; - assign prep_gen_adata_null = (cmdreq_data.cmd == GEN) && (cmdreq_data.pdata == '0); + assign prep_gen_adata_null = (req_data.cmd == GEN) && (req_data.pdata == '0); - assign gen_adata_null_d = !enable_i ? '0 : prep_gen_adata_null; + assign gen_adata_null_d = !enable_i ? 1'b0 : + ((req_vld_i && req_rdy_o) ? prep_gen_adata_null : gen_adata_null_q); // send to the update block - assign update_req_vld_o = sfifo_cmdreq_rvld && !prep_gen_adata_null; + assign update_req_vld_o = req_vld_i && !prep_gen_adata_null; assign update_req_data_o = '{ - inst_id: cmdreq_data.inst_id, - cmd: cmdreq_data.cmd, + inst_id: req_data.inst_id, + cmd: req_data.cmd, key: prep_key, v: prep_v, pdata: prep_seed_material @@ -227,19 +175,19 @@ module csrng_ctr_drbg_cmd import csrng_pkg::*; ( ); always_comb begin - rcstage_core_data_fifo = cmdreq_data; + rcstage_core_data_fifo = req_data; rcstage_core_data_fifo.key = prep_key; rcstage_core_data_fifo.v = prep_v; rcstage_core_data_fifo.rs_ctr = prep_rc; end - assign sfifo_rcstage_wdata = {cmdreq_glast, + assign sfifo_rcstage_wdata = {req_glast_i, rcstage_core_data_fifo}; assign {rcstage_glast, rcstage_data} = sfifo_rcstage_rdata; - assign sfifo_rcstage_wvld = sfifo_cmdreq_rrdy; + assign sfifo_rcstage_wvld = req_vld_i && req_rdy_o; assign sfifo_rcstage_rrdy = sfifo_rcstage_rvld && (update_rsp_vld_i || gen_adata_null_q); assign update_rsp_rdy_o = sfifo_rcstage_rvld && sfifo_keyvrc_wrdy; diff --git a/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv b/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv index 9f0ed41be0645..45ea1253941ca 100644 --- a/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv +++ b/hw/ip/csrng/rtl/csrng_ctr_drbg_upd.sv @@ -41,34 +41,13 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( // Error status outputs output logic ctr_err_o, - output logic [2:0] fifo_updreq_err_o, - output logic [2:0] fifo_bencreq_err_o, output logic [2:0] fifo_bencack_err_o, - output logic [2:0] fifo_pdata_err_o, output logic [2:0] fifo_final_err_o, output logic sm_block_enc_req_err_o, output logic sm_block_enc_rsp_err_o ); // signals - // updreq fifo - logic sfifo_updreq_wvld; - logic sfifo_updreq_wrdy; - logic [UpdDataWidth-1:0] sfifo_updreq_wdata; - logic sfifo_updreq_rvld; - logic sfifo_updreq_rrdy; - logic [UpdDataWidth-1:0] sfifo_updreq_rdata; - - csrng_upd_data_t req_data_fifo; - - // blk_encrypt_req fifo - logic sfifo_bencreq_wvld; - logic sfifo_bencreq_wrdy; - logic [BencDataWidth-1:0] sfifo_bencreq_rdata; - logic sfifo_bencreq_rvld; - logic sfifo_bencreq_rrdy; - logic [BencDataWidth-1:0] sfifo_bencreq_wdata; - // blk_encrypt_ack fifo logic sfifo_bencack_wvld; logic sfifo_bencack_wrdy; @@ -79,14 +58,6 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( csrng_benc_data_t benc_rsp_data_fifo; - // pdata_stage fifo - logic sfifo_pdata_wvld; - logic sfifo_pdata_wrdy; - logic [SeedLen-1:0] sfifo_pdata_wdata; - logic sfifo_pdata_rvld; - logic sfifo_pdata_rrdy; - logic [SeedLen-1:0] sfifo_pdata_rdata; - // key_v fifo logic sfifo_final_wvld; logic sfifo_final_wrdy; @@ -115,30 +86,32 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( logic [InstIdWidth-1:0] concat_inst_id_q, concat_inst_id_d; // Encoding generated with: - // $ ./util/design/sparse-fsm-encode.py -d 3 -m 4 -n 5 \ - // -s 47328894 --language=sv + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 5 -n 6 \ + // -s 47377994 --language=sv // // Hamming distance histogram: // // 0: -- // 1: -- // 2: -- - // 3: |||||||||||||||||||| (66.67%) - // 4: |||||||||| (33.33%) - // 5: -- + // 3: |||||||||||||||||||| (50.00%) + // 4: |||||||||||||||| (40.00%) + // 5: |||| (10.00%) + // 6: -- // // Minimum Hamming distance: 3 - // Maximum Hamming distance: 4 + // Maximum Hamming distance: 5 // Minimum Hamming weight: 2 - // Maximum Hamming weight: 3 + // Maximum Hamming weight: 5 // - localparam int BlkEncStateWidth = 5; + localparam int BlkEncStateWidth = 6; typedef enum logic [BlkEncStateWidth-1:0] { - ReqIdle = 5'b11000, - ReqSend = 5'b10011, - ESHalt = 5'b01110, - BEError = 5'b00101 + ReqIdle = 6'b111011, + ReqSend = 6'b000111, + ReqWait = 6'b001010, + ESHalt = 6'b010100, + BEError = 6'b101101 } blk_enc_state_e; blk_enc_state_e blk_enc_state_d, blk_enc_state_q; @@ -197,41 +170,6 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( end end - //-------------------------------------------- - // input request fifo for staging update requests - //-------------------------------------------- - - prim_fifo_sync #( - .Width(UpdDataWidth), - .Pass(0), - .Depth(1), - .OutputZeroIfEmpty(1'b0) - ) u_prim_fifo_sync_updreq ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .clr_i (!enable_i), - .wvalid_i(sfifo_updreq_wvld), - .wready_o(sfifo_updreq_wrdy), - .wdata_i (sfifo_updreq_wdata), - .rvalid_o(sfifo_updreq_rvld), - .rready_i(sfifo_updreq_rrdy), - .rdata_o (sfifo_updreq_rdata), - .full_o (), - .depth_o (), - .err_o () - ); - - assign sfifo_updreq_wvld = sfifo_updreq_wrdy && req_vld_i; - assign sfifo_updreq_wdata = req_data_i; - assign req_rdy_o = sfifo_updreq_wrdy; - - assign req_data_fifo = sfifo_updreq_rdata; - - assign fifo_updreq_err_o = { - ( sfifo_updreq_wvld && !sfifo_updreq_wrdy), - ( sfifo_updreq_rrdy && !sfifo_updreq_rvld), - (!sfifo_updreq_wrdy && !sfifo_updreq_rvld)}; - //-------------------------------------------- // prepare value for block_encrypt step //-------------------------------------------- @@ -240,10 +178,10 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( // violates the redundant counter encoding listed as a SEC_CM below. if (CtrLen < BlkLen) begin : g_ctr_load_lsb logic [CtrLen-1:0] v_inc; - assign v_inc = req_data_fifo.v[CtrLen-1:0] + 1; - assign v_load = {req_data_fifo.v[BlkLen-1:CtrLen], v_inc}; + assign v_inc = req_data_i.v[CtrLen-1:0] + 1; + assign v_load = {req_data_i.v[BlkLen-1:CtrLen], v_inc}; end else begin : g_ctr_load_full - assign v_load = req_data_fifo.v + 1; + assign v_load = req_data_i.v + 1; end // SEC_CM: DRBG_UPD.CTR.REDUN @@ -302,9 +240,7 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( blk_enc_state_d = blk_enc_state_q; v_ctr_load = 1'b0; v_ctr_inc = 1'b0; - sfifo_pdata_wvld = 1'b0; - sfifo_bencreq_wvld = 1'b0; - sfifo_updreq_rrdy = 1'b0; + block_encrypt_req_vld_o = 1'b0; sm_block_enc_req_err_o = 1'b0; es_halt_ack_o = 1'b0; unique case (blk_enc_state_q) @@ -316,9 +252,8 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( blk_enc_state_d = ESHalt; end else if (!enable_i) begin blk_enc_state_d = ReqIdle; - end else if (sfifo_updreq_rvld && sfifo_bencreq_wrdy && sfifo_pdata_wrdy) begin + end else if (req_vld_i) begin v_ctr_load = 1'b1; - sfifo_pdata_wvld = 1'b1; blk_enc_state_d = ReqSend; end end @@ -326,12 +261,24 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( if (!enable_i) begin blk_enc_state_d = ReqIdle; end else if (!block_ctr_done) begin - if (sfifo_bencreq_wrdy) begin + block_encrypt_req_vld_o = 1'b1; + if (block_encrypt_req_rdy_i) begin v_ctr_inc = 1'b1; - sfifo_bencreq_wvld = 1'b1; end end else begin - sfifo_updreq_rrdy = 1'b1; + // Wait for completion on the benc_rsp path + if (req_vld_i && req_rdy_o) begin + blk_enc_state_d = ReqIdle; + end else begin + blk_enc_state_d = ReqWait; + end + end + end + ReqWait: begin + if (!enable_i) begin + blk_enc_state_d = ReqIdle; + end else if (req_vld_i && req_rdy_o) begin + // Wait for completion on the benc_rsp path blk_enc_state_d = ReqIdle; end end @@ -351,46 +298,11 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( endcase end - //-------------------------------------------- - // block_encrypt request fifo for staging aes requests - //-------------------------------------------- - - prim_fifo_sync #( - .Width(BencDataWidth), - .Pass(0), - .Depth(1), - .OutputZeroIfEmpty(1'b0) - ) u_prim_fifo_sync_bencreq ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .clr_i (!enable_i), - .wvalid_i(sfifo_bencreq_wvld), - .wready_o(sfifo_bencreq_wrdy), - .wdata_i (sfifo_bencreq_wdata), - .rvalid_o(sfifo_bencreq_rvld), - .rready_i(sfifo_bencreq_rrdy), - .rdata_o (sfifo_bencreq_rdata), - .full_o (), - .depth_o (), - .err_o () - ); - - assign sfifo_bencreq_rrdy = sfifo_bencreq_rvld && block_encrypt_req_rdy_i; - assign block_encrypt_req_vld_o = sfifo_bencreq_rvld; - // Forward the upstream data together with the current counter value to block_encrypt - assign sfifo_bencreq_wdata = {req_data_fifo.inst_id, - req_data_fifo.cmd, - req_data_fifo.key, - v_ctr_sized}; - - // rdata of the FIFO is already in the correct format - assign block_encrypt_req_data_o = sfifo_bencreq_rdata; - - assign fifo_bencreq_err_o = - {( sfifo_bencreq_wvld && !sfifo_bencreq_wrdy), - ( sfifo_bencreq_rrdy && !sfifo_bencreq_rvld), - (!sfifo_bencreq_wrdy && !sfifo_bencreq_rvld)}; + assign block_encrypt_req_data_o = {req_data_i.inst_id, + req_data_i.cmd, + req_data_i.key, + v_ctr_sized}; //-------------------------------------------- // block_encrypt response fifo from block encrypt @@ -427,37 +339,6 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( ( sfifo_bencack_rrdy && !sfifo_bencack_rvld), (!sfifo_bencack_wrdy && !sfifo_bencack_rvld)}; - //-------------------------------------------- - // fifo to stage provided_data, waiting for blk_encrypt to ack - //-------------------------------------------- - - prim_fifo_sync #( - .Width(SeedLen), - .Pass(0), - .Depth(1), - .OutputZeroIfEmpty(1'b0) - ) u_prim_fifo_sync_pdata ( - .clk_i (clk_i), - .rst_ni (rst_ni), - .clr_i (!enable_i), - .wvalid_i(sfifo_pdata_wvld), - .wready_o(sfifo_pdata_wrdy), - .wdata_i (sfifo_pdata_wdata), - .rvalid_o(sfifo_pdata_rvld), - .rready_i(sfifo_pdata_rrdy), - .rdata_o (sfifo_pdata_rdata), - .full_o (), - .depth_o (), - .err_o () - ); - - assign sfifo_pdata_wdata = req_data_fifo.pdata; - - assign fifo_pdata_err_o = - {( sfifo_pdata_wvld && !sfifo_pdata_wrdy), - ( sfifo_pdata_rrdy && !sfifo_pdata_rvld), - (!sfifo_pdata_wrdy && !sfifo_pdata_rvld)}; - //-------------------------------------------- // shifting logic to receive values from block_encrypt //-------------------------------------------- @@ -505,16 +386,16 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( outblk_state_d = outblk_state_q; concat_ctr_inc = 1'b0; concat_outblk_shift = 1'b0; - sfifo_pdata_rrdy = 1'b0; sfifo_bencack_rrdy = 1'b0; sfifo_final_wvld = 1'b0; + req_rdy_o = 1'b0; sm_block_enc_rsp_err_o = 1'b0; unique case (outblk_state_q) // AckIdle: increment v this cycle, push in next AckIdle: begin if (!enable_i) begin outblk_state_d = AckIdle; - end else if (sfifo_bencack_rvld && sfifo_pdata_rvld && sfifo_final_wrdy) begin + end else if (sfifo_bencack_rvld && sfifo_final_wrdy) begin outblk_state_d = Load; end end @@ -531,8 +412,8 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( if (!enable_i) begin outblk_state_d = AckIdle; end else if (concat_ctr_done) begin - sfifo_pdata_rrdy = 1'b1; - sfifo_final_wvld = 1'b1; + req_rdy_o = 1'b1; + sfifo_final_wvld = 1'b1; outblk_state_d = AckIdle; end else begin concat_outblk_shift = 1'b1; @@ -555,7 +436,7 @@ module csrng_ctr_drbg_upd import csrng_pkg::*; ( //-------------------------------------------- // XOR the additional data with the new key and value from block encryption - assign updated_key_and_v = concat_outblk_q ^ sfifo_pdata_rdata; + assign updated_key_and_v = concat_outblk_q ^ req_data_i.pdata; prim_fifo_sync #( .Width(BencDataWidth), diff --git a/hw/ip/csrng/rtl/csrng_main_sm.sv b/hw/ip/csrng/rtl/csrng_main_sm.sv index 05874109445bc..2cf617c5f38d2 100644 --- a/hw/ip/csrng/rtl/csrng_main_sm.sv +++ b/hw/ip/csrng/rtl/csrng_main_sm.sv @@ -9,26 +9,27 @@ `include "prim_assert.sv" module csrng_main_sm import csrng_pkg::*; ( - input logic clk_i, - input logic rst_ni, + input logic clk_i, + input logic rst_ni, + input logic enable_i, - input logic enable_i, - input logic acmd_avail_i, + input logic acmd_avail_i, output logic acmd_accept_o, - input logic [2:0] acmd_i, - input logic acmd_eop_i, - input logic ctr_drbg_cmd_req_rdy_i, - input logic flag0_i, + input acmd_e acmd_i, + input logic acmd_eop_i, + + input logic flag0_i, + output logic cmd_entropy_req_o, - input logic cmd_entropy_avail_i, - output logic instant_req_o, - output logic reseed_req_o, - output logic generate_req_o, - output logic update_req_o, - output logic uninstant_req_o, + input logic cmd_entropy_avail_i, + + output logic cmd_vld_o, + input logic cmd_rdy_i, output logic clr_adata_packer_o, - input logic cmd_complete_i, - input logic local_escalate_i, + input logic cmd_complete_i, + + input logic local_escalate_i, + output logic [MainSmStateWidth-1:0] main_sm_state_o, output logic main_sm_err_o ); @@ -42,11 +43,7 @@ module csrng_main_sm import csrng_pkg::*; ( state_d = state_q; acmd_accept_o = 1'b0; cmd_entropy_req_o = 1'b0; - instant_req_o = 1'b0; - reseed_req_o = 1'b0; - generate_req_o = 1'b0; - update_req_o = 1'b0; - uninstant_req_o = 1'b0; + cmd_vld_o = 1'b0; clr_adata_packer_o = 1'b0; main_sm_err_o = 1'b0; @@ -56,11 +53,8 @@ module csrng_main_sm import csrng_pkg::*; ( end else if (local_escalate_i) begin // In case local escalate is high we must transition to the error state. state_d = MainSmError; - end else if (!enable_i && state_q inside {MainSmIdle, MainSmParseCmd, MainSmInstantPrep, - MainSmInstantReq, MainSmReseedPrep, MainSmReseedReq, - MainSmGeneratePrep, MainSmGenerateReq, - MainSmUpdatePrep, MainSmUpdateReq, - MainSmUninstantPrep, MainSmUninstantReq, + end else if (!enable_i && state_q inside {MainSmIdle, MainSmParseCmd, MainSmEntropyReq, + MainSmCmdPrep, MainSmCmdVld, MainSmClrAData, MainSmCmdCompWait}) begin // In case the module is disabled and we are in a legal state we must go into idle state. state_d = MainSmIdle; @@ -68,88 +62,40 @@ module csrng_main_sm import csrng_pkg::*; ( // Otherwise do the state machine as normal. unique case (state_q) MainSmIdle: begin - // Because of the if statement above we won't leave idle if enable is low. - if (ctr_drbg_cmd_req_rdy_i) begin - // Signal the arbiter to grant this request. - if (acmd_avail_i) begin - acmd_accept_o = 1'b1; - state_d = MainSmParseCmd; - end + // Signal the arbiter to grant this request. + if (acmd_avail_i) begin + acmd_accept_o = 1'b1; + state_d = MainSmParseCmd; end end MainSmParseCmd: begin - if (ctr_drbg_cmd_req_rdy_i && acmd_eop_i) begin - if (acmd_i == INS) begin - state_d = MainSmInstantPrep; - end else if (acmd_i == RES) begin - state_d = MainSmReseedPrep; - end else if (acmd_i == GEN) begin - state_d = MainSmGeneratePrep; - end else if (acmd_i == UPD) begin - state_d = MainSmUpdatePrep; - end else if (acmd_i == UNI) begin - state_d = MainSmUninstantPrep; - end else begin - // Command was not supported. - state_d = MainSmIdle; - end - end - end - MainSmInstantPrep: begin - if (flag0_i) begin - // Assumes all adata is present now. - state_d = MainSmInstantReq; - end else begin - // Delay one clock to fix timing issue. - cmd_entropy_req_o = 1'b1; - if (cmd_entropy_avail_i) begin - state_d = MainSmInstantReq; - end + if (acmd_eop_i) begin + unique case (acmd_i) + INS, RES: state_d = MainSmEntropyReq; // Command may require entropy + GEN, UPD, UNI: state_d = MainSmCmdPrep; // Command does not require entropy + default: state_d = MainSmIdle; // Command was not supported + endcase end end - MainSmInstantReq: begin - instant_req_o = 1'b1; - state_d = MainSmClrAData; - end - MainSmReseedPrep: begin + MainSmEntropyReq: begin if (flag0_i) begin - // Assumes all adata is present now. - state_d = MainSmReseedReq; + // With flag0 set, no entropy is required. + state_d = MainSmCmdVld; end else begin // Delay one clock to fix timing issue. cmd_entropy_req_o = 1'b1; if (cmd_entropy_avail_i) begin - state_d = MainSmReseedReq; + state_d = MainSmCmdVld; end end end - MainSmReseedReq: begin - reseed_req_o = 1'b1; - state_d = MainSmClrAData; - end - MainSmGeneratePrep: begin - // Assumes all adata is present now. - state_d = MainSmGenerateReq; - end - MainSmGenerateReq: begin - generate_req_o = 1'b1; - state_d = MainSmClrAData; - end - MainSmUpdatePrep: begin - // Assumes all adata is present now. - state_d = MainSmUpdateReq; - end - MainSmUpdateReq: begin - update_req_o = 1'b1; - state_d = MainSmClrAData; - end - MainSmUninstantPrep: begin + MainSmCmdPrep: begin // Assumes all adata is present now. - state_d = MainSmUninstantReq; + state_d = MainSmCmdVld; end - MainSmUninstantReq: begin - uninstant_req_o = 1'b1; - state_d = MainSmClrAData; + MainSmCmdVld: begin + cmd_vld_o = 1'b1; + if (cmd_rdy_i) state_d = MainSmClrAData; end MainSmClrAData: begin clr_adata_packer_o = 1'b1; @@ -174,4 +120,5 @@ module csrng_main_sm import csrng_pkg::*; ( `ASSERT(CsrngMainErrorStStable_A, state_q == MainSmError |=> $stable(state_q)) // If in error state, the error output must be high. `ASSERT(CsrngMainErrorOutput_A, state_q == MainSmError |-> main_sm_err_o) + endmodule diff --git a/hw/ip/csrng/rtl/csrng_pkg.sv b/hw/ip/csrng/rtl/csrng_pkg.sv index 839f30e946e32..61ec91cce7c6d 100644 --- a/hw/ip/csrng/rtl/csrng_pkg.sv +++ b/hw/ip/csrng/rtl/csrng_pkg.sv @@ -22,6 +22,9 @@ package csrng_pkg; parameter int unsigned CtrLen = 32; parameter int unsigned RsCtrWidth = 32; + // Width of the counter in the command stages to count the amount of generated random bits + parameter int unsigned GenBitsCtrWidth = 12; + // Commonly used internal signal widths parameter int unsigned CmdWidth = 3; parameter int unsigned InstIdWidth = 4; @@ -137,45 +140,36 @@ package csrng_pkg; parameter int unsigned BencDataWidth = $bits(csrng_benc_data_t); parameter int unsigned StateWidth = $bits(csrng_state_t); - parameter int unsigned MainSmStateWidth = 8; + parameter int unsigned MainSmStateWidth = 6; // Encoding generated with: - // $ ./util/design/sparse-fsm-encode.py -d 3 -m 15 -n 8 \ - // -s 1300573258 --language=sv + // $ ./util/design/sparse-fsm-encode.py -d 3 -m 8 -n 6 \ + // -s 137328258 --language=sv // // Hamming distance histogram: // // 0: -- // 1: -- // 2: -- - // 3: |||||||||||||||||| (32.38%) - // 4: |||||||||||||||||||| (35.24%) - // 5: |||||||| (15.24%) - // 6: |||||| (11.43%) - // 7: ||| (5.71%) - // 8: -- + // 3: |||||||||||||||||||| (57.14%) + // 4: ||||||||||||||| (42.86%) + // 5: -- + // 6: -- // // Minimum Hamming distance: 3 - // Maximum Hamming distance: 7 + // Maximum Hamming distance: 4 // Minimum Hamming weight: 1 - // Maximum Hamming weight: 7 + // Maximum Hamming weight: 5 // typedef enum logic [MainSmStateWidth-1:0] { - MainSmIdle = 8'b01001110, // idle - MainSmParseCmd = 8'b10111011, // parse the cmd - MainSmInstantPrep = 8'b11000001, // instantiate prep - MainSmInstantReq = 8'b01010100, // instantiate request (takes adata or entropy) - MainSmReseedPrep = 8'b11011101, // reseed prep - MainSmReseedReq = 8'b01011011, // reseed request (takes adata and entropy and Key,V,RC) - MainSmGeneratePrep = 8'b11101111, // generate request (takes adata? and Key,V,RC) - MainSmGenerateReq = 8'b00100100, // generate request (takes adata? and Key,V,RC) - MainSmUpdatePrep = 8'b00110001, // update prep - MainSmUpdateReq = 8'b10010000, // update request (takes adata and Key,V,RC) - MainSmUninstantPrep = 8'b11110110, // uninstantiate prep - MainSmUninstantReq = 8'b01100011, // uninstantiate request - MainSmClrAData = 8'b00000010, // clear out the additional data packer fifo - MainSmCmdCompWait = 8'b10111100, // wait for command to complete - MainSmError = 8'b01111000 // error state, results in fatal alert + MainSmIdle = 6'b110111, // idle + MainSmParseCmd = 6'b011101, // parse the cmd + MainSmEntropyReq = 6'b001110, // request entropy if necessary + MainSmCmdPrep = 6'b000011, // delay cycle for command request (?) + MainSmCmdVld = 6'b010000, // command request to core data path + MainSmClrAData = 6'b111010, // clear out the additional data packer fifo + MainSmCmdCompWait = 6'b100100, // wait for command to complete + MainSmError = 6'b101001 // error state, results in fatal alert } main_sm_state_e; parameter int CsKeymgrDivWidth = 384; diff --git a/hw/ip/csrng/rtl/csrng_reg_pkg.sv b/hw/ip/csrng/rtl/csrng_reg_pkg.sv index fa9441e7ed1b6..626f0439f0d99 100644 --- a/hw/ip/csrng/rtl/csrng_reg_pkg.sv +++ b/hw/ip/csrng/rtl/csrng_reg_pkg.sv @@ -307,22 +307,10 @@ package csrng_reg_pkg; logic d; logic de; } sfifo_final_err; - struct packed { - logic d; - logic de; - } sfifo_pdata_err; struct packed { logic d; logic de; } sfifo_bencack_err; - struct packed { - logic d; - logic de; - } sfifo_bencreq_err; - struct packed { - logic d; - logic de; - } sfifo_updreq_err; struct packed { logic d; logic de; @@ -331,10 +319,6 @@ package csrng_reg_pkg; logic d; logic de; } sfifo_rcstage_err; - struct packed { - logic d; - logic de; - } sfifo_cmdreq_err; struct packed { logic d; logic de; @@ -346,7 +330,7 @@ package csrng_reg_pkg; } csrng_hw2reg_err_code_reg_t; typedef struct packed { - logic [7:0] d; + logic [5:0] d; logic de; } csrng_hw2reg_main_sm_state_reg_t; @@ -369,16 +353,16 @@ package csrng_reg_pkg; // HW -> register type typedef struct packed { - csrng_hw2reg_intr_state_reg_t intr_state; // [273:266] - csrng_hw2reg_reseed_counter_mreg_t [2:0] reseed_counter; // [265:170] - csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [169:162] - csrng_hw2reg_genbits_vld_reg_t genbits_vld; // [161:160] - csrng_hw2reg_genbits_reg_t genbits; // [159:128] - csrng_hw2reg_int_state_val_reg_t int_state_val; // [127:96] - csrng_hw2reg_hw_exc_sts_reg_t hw_exc_sts; // [95:79] - csrng_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [78:61] - csrng_hw2reg_err_code_reg_t err_code; // [60:9] - csrng_hw2reg_main_sm_state_reg_t main_sm_state; // [8:0] + csrng_hw2reg_intr_state_reg_t intr_state; // [263:256] + csrng_hw2reg_reseed_counter_mreg_t [2:0] reseed_counter; // [255:160] + csrng_hw2reg_sw_cmd_sts_reg_t sw_cmd_sts; // [159:152] + csrng_hw2reg_genbits_vld_reg_t genbits_vld; // [151:150] + csrng_hw2reg_genbits_reg_t genbits; // [149:118] + csrng_hw2reg_int_state_val_reg_t int_state_val; // [117:86] + csrng_hw2reg_hw_exc_sts_reg_t hw_exc_sts; // [85:69] + csrng_hw2reg_recov_alert_sts_reg_t recov_alert_sts; // [68:51] + csrng_hw2reg_err_code_reg_t err_code; // [50:7] + csrng_hw2reg_main_sm_state_reg_t main_sm_state; // [6:0] } csrng_hw2reg_t; // Register offsets diff --git a/hw/ip/csrng/rtl/csrng_reg_top.sv b/hw/ip/csrng/rtl/csrng_reg_top.sv index f134307371a37..b431701e1bac7 100644 --- a/hw/ip/csrng/rtl/csrng_reg_top.sv +++ b/hw/ip/csrng/rtl/csrng_reg_top.sv @@ -216,13 +216,9 @@ module csrng_reg_top ( logic recov_alert_sts_cmd_stage_reseed_cnt_alert_wd; logic err_code_sfifo_cmd_err_qs; logic err_code_sfifo_genbits_err_qs; - logic err_code_sfifo_cmdreq_err_qs; logic err_code_sfifo_rcstage_err_qs; logic err_code_sfifo_keyvrc_err_qs; - logic err_code_sfifo_updreq_err_qs; - logic err_code_sfifo_bencreq_err_qs; logic err_code_sfifo_bencack_err_qs; - logic err_code_sfifo_pdata_err_qs; logic err_code_sfifo_final_err_qs; logic err_code_sfifo_gbencack_err_qs; logic err_code_sfifo_grcstage_err_qs; @@ -243,7 +239,7 @@ module csrng_reg_top ( logic err_code_test_we; logic [4:0] err_code_test_qs; logic [4:0] err_code_test_wd; - logic [7:0] main_sm_state_qs; + logic [5:0] main_sm_state_qs; // Register instances // R[intr_state]: V(False) @@ -1450,33 +1446,6 @@ module csrng_reg_top ( .qs (err_code_sfifo_genbits_err_qs) ); - // F[sfifo_cmdreq_err]: 2:2 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_err_code_sfifo_cmdreq_err ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.err_code.sfifo_cmdreq_err.de), - .d (hw2reg.err_code.sfifo_cmdreq_err.d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (err_code_sfifo_cmdreq_err_qs) - ); - // F[sfifo_rcstage_err]: 3:3 prim_subreg #( .DW (1), @@ -1531,60 +1500,6 @@ module csrng_reg_top ( .qs (err_code_sfifo_keyvrc_err_qs) ); - // F[sfifo_updreq_err]: 5:5 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_err_code_sfifo_updreq_err ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.err_code.sfifo_updreq_err.de), - .d (hw2reg.err_code.sfifo_updreq_err.d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (err_code_sfifo_updreq_err_qs) - ); - - // F[sfifo_bencreq_err]: 6:6 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_err_code_sfifo_bencreq_err ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.err_code.sfifo_bencreq_err.de), - .d (hw2reg.err_code.sfifo_bencreq_err.d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (err_code_sfifo_bencreq_err_qs) - ); - // F[sfifo_bencack_err]: 7:7 prim_subreg #( .DW (1), @@ -1612,33 +1527,6 @@ module csrng_reg_top ( .qs (err_code_sfifo_bencack_err_qs) ); - // F[sfifo_pdata_err]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_err_code_sfifo_pdata_err ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.err_code.sfifo_pdata_err.de), - .d (hw2reg.err_code.sfifo_pdata_err.d), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (err_code_sfifo_pdata_err_qs) - ); - // F[sfifo_final_err]: 9:9 prim_subreg #( .DW (1), @@ -2144,9 +2032,9 @@ module csrng_reg_top ( // R[main_sm_state]: V(False) prim_subreg #( - .DW (8), + .DW (6), .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (8'h4e), + .RESVAL (6'h37), .Mubi (1'b0) ) u_main_sm_state ( .clk_i (clk_i), @@ -2468,13 +2356,9 @@ module csrng_reg_top ( addr_hit[21]: begin reg_rdata_next[0] = err_code_sfifo_cmd_err_qs; reg_rdata_next[1] = err_code_sfifo_genbits_err_qs; - reg_rdata_next[2] = err_code_sfifo_cmdreq_err_qs; reg_rdata_next[3] = err_code_sfifo_rcstage_err_qs; reg_rdata_next[4] = err_code_sfifo_keyvrc_err_qs; - reg_rdata_next[5] = err_code_sfifo_updreq_err_qs; - reg_rdata_next[6] = err_code_sfifo_bencreq_err_qs; reg_rdata_next[7] = err_code_sfifo_bencack_err_qs; - reg_rdata_next[8] = err_code_sfifo_pdata_err_qs; reg_rdata_next[9] = err_code_sfifo_final_err_qs; reg_rdata_next[10] = err_code_sfifo_gbencack_err_qs; reg_rdata_next[11] = err_code_sfifo_grcstage_err_qs; @@ -2499,7 +2383,7 @@ module csrng_reg_top ( end addr_hit[23]: begin - reg_rdata_next[7:0] = main_sm_state_qs; + reg_rdata_next[5:0] = main_sm_state_qs; end default: begin diff --git a/sw/device/lib/dif/dif_csrng.c b/sw/device/lib/dif/dif_csrng.c index ac353fb8d5e6b..7727c207a97c0 100644 --- a/sw/device/lib/dif/dif_csrng.c +++ b/sw/device/lib/dif/dif_csrng.c @@ -184,27 +184,15 @@ dif_result_t dif_csrng_get_cmd_force_unhealthy_fifo(const dif_csrng_t *csrng, case kDifCsrngFifoGenBits: fifo_bit = CSRNG_ERR_CODE_SFIFO_GENBITS_ERR_BIT; break; - case kDifCsrngFifoCmdReq: - fifo_bit = CSRNG_ERR_CODE_SFIFO_CMDREQ_ERR_BIT; - break; case kDifCsrngFifoRcStage: fifo_bit = CSRNG_ERR_CODE_SFIFO_RCSTAGE_ERR_BIT; break; case kDifCsrngFifoKeyVrc: fifo_bit = CSRNG_ERR_CODE_SFIFO_KEYVRC_ERR_BIT; break; - case kDifCsrngFifoUpdateReq: - fifo_bit = CSRNG_ERR_CODE_SFIFO_UPDREQ_ERR_BIT; - break; - case kDifCsrngFifoBencRec: - fifo_bit = CSRNG_ERR_CODE_SFIFO_BENCREQ_ERR_BIT; - break; case kDifCsrngFifoBencAck: fifo_bit = CSRNG_ERR_CODE_SFIFO_BENCACK_ERR_BIT; break; - case kDifCsrngFifoPData: - fifo_bit = CSRNG_ERR_CODE_SFIFO_PDATA_ERR_BIT; - break; case kDifCsrngFifoFinal: fifo_bit = CSRNG_ERR_CODE_SFIFO_FINAL_ERR_BIT; break; diff --git a/sw/device/lib/dif/dif_csrng.h b/sw/device/lib/dif/dif_csrng.h index cb44550181c49..53b7a361a7d8c 100644 --- a/sw/device/lib/dif/dif_csrng.h +++ b/sw/device/lib/dif/dif_csrng.h @@ -93,13 +93,9 @@ typedef enum dif_csrng_cmd_status_kind { typedef enum dif_csrng_fifo { kDifCsrngFifoCmd, kDifCsrngFifoGenBits, - kDifCsrngFifoCmdReq, kDifCsrngFifoRcStage, kDifCsrngFifoKeyVrc, - kDifCsrngFifoUpdateReq, - kDifCsrngFifoBencRec, kDifCsrngFifoBencAck, - kDifCsrngFifoPData, kDifCsrngFifoFinal, kDifCsrngFifoGBencAck, kDifCsrngFifoGrcStage,