bump version number, update changelog

catharanthus · catharanthus · commit 94e6b638d314 · 2021-10-21T20:42:58.000+03:00
diff --git a/doc/lxp32-trm.pdf b/doc/lxp32-trm.pdf
diff --git a/doc/src/trm/frontmatter.tex b/doc/src/trm/frontmatter.tex
@@ -15,7 +15,7 @@
 	\Large a lightweight open source 32-bit CPU core\par
 	\LARGE \textbf{Technical Reference Manual}\par
 	\vspace{1.2\onelineskip}
-	\large Version 1.1\par
+	\large Version 1.2\par
 	\vspace*{4\onelineskip}
 	\end{center}
 	\vspace*{\fill}
diff --git a/doc/src/trm/lxp32-trm.tex b/doc/src/trm/lxp32-trm.tex
@@ -1828,6 +1828,17 @@ \section{Data bus}
 
 \chapter{List of changes}
 
+\section*{Version 1.2 (2021-10-21)}
+
+This release introduces a few non-breaking changes to the software and testbench. The CPU RTL description hasn't been changed from the previous release.
+
+\begin{itemize}
+	\item \shellcmd{lxp32asm} now supports C-style conditional processing directives: \instr{\#ifdef}, \instr{\#ifndef}, \instr{\#else} and \instr{\#endif}.
+	\item \instr{\#define} directive can now declare a macro with zero subsitute tokens.
+	\item A new \instr{\#error} directive.
+	\item Minor changes to the testbench.
+\end{itemize}
+
 \section*{Version 1.1 (2019-01-11)}
 
 This release introduces a minor but technically breaking hardware change: the START\_ADDR generic, which used to be 30-bit, has been for convenience extended to a full 32-bit word; the two least significant bits are ignored.
