tb: improve interrupt trigger mode test

Author: catharanthus

verify/lxp32/src/firmware/test021.asm

@@ -1,29 +1,91 @@
 /*
- * This test verifies level-sensitive interrupt handling
+ * This test verifies various interrupt trigger modes
  */
 
 	lc r100, 0x10000000 // test result output pointer
 	lc r101, halt
 	lc r102, failure
 	lc r103, 0x40000000 // timer: number of pulses (0xFFFFFFFF - infinite)
 	lc r104, 0x40000004 // timer: delay between pulses (in cycles)
-	lc r105, 0x40000008 // timer: clear interrupt
-	
-	lc iv3, timer_handler
-	lc cr, 0x08080008 // enable intertups 3, mark as level-sensitive and inverted
+	lc r105, 0x40000008 // timer: trigger mode
+	lc r106, 0x4000000C // timer: clear interrupt
+
+// Rising edge trigger
+	mov cr, 0
+	lc iv3, timer_handler_edge
+	sw r105, 0
+	lc cr, 0x00000008 // enable interrupt
 	
 	lc r32, 1000 // cycle counter
-	lc r33, cnt_loop
+	lc r33, cnt_loop1
 	mov r34, 0 // interrupt call counter
 	
 	sw r104, 100
-	sw r103, 5
+	sw r103, 3
 	
-cnt_loop:
+cnt_loop1:
 	sub r32, r32, 1
 	cjmpug r33, r32, 0 // cnt_loop
 	
+	cjmpne r102, r34, 3 // failure
+
+// Falling edge trigger
+	mov cr, 0
+	lc iv3, timer_handler_edge
+	sw r105, 2
+	lc cr, 0x08000008 // enable interrupt
+
+	lc r32, 1000 // cycle counter
+	lc r33, cnt_loop2
+	mov r34, 0 // interrupt call counter
+
+	sw r104, 100
+	sw r103, 4
+
+cnt_loop2:
+	sub r32, r32, 1
+	cjmpug r33, r32, 0 // cnt_loop
+
+	cjmpne r102, r34, 4 // failure
+
+// High level trigger
+	mov cr, 0
+	lc iv3, timer_handler_level
+	sw r105, 1
+	lc cr, 0x00080008 // enable interrupt
+
+	lc r32, 1000 // cycle counter
+	lc r33, cnt_loop3
+	mov r34, 0 // interrupt call counter
+
+	sw r104, 100
+	sw r103, 5
+
+cnt_loop3:
+	sub r32, r32, 1
+	cjmpug r33, r32, 0 // cnt_loop
+
 	cjmpne r102, r34, 5 // failure
+
+// Low level trigger
+	mov cr, 0
+	lc iv3, timer_handler_level
+	sw r105, 3
+	lc cr, 0x08080008 // enable interrupt
+
+	lc r32, 1000 // cycle counter
+	lc r33, cnt_loop4
+	mov r34, 0 // interrupt call counter
+
+	sw r104, 100
+	sw r103, 6
+
+cnt_loop4:
+	sub r32, r32, 1
+	cjmpug r33, r32, 0 // cnt_loop
+
+	cjmpne r102, r34, 6 // failure
+
 	
 	sw r100, 1
 	jmp r101 // halt
@@ -35,9 +97,15 @@ halt:
 	hlt
 	jmp r101 // halt
 	
-timer_handler:
+timer_handler_edge:
 	add r34, r34, 1
-	sw r105, 1
+	lc r0, 0x10000004
+	sw r0, r34
+	iret
+
+timer_handler_level:
+	add r34, r34, 1
+	sw r106, 1
 	lc r0, 0x10000004
 	sw r0, r34
 	iret

verify/lxp32/src/platform/platform.vhd

@@ -349,10 +349,6 @@ timer_inst: entity work.timer(rtl)
 -- Timer with a level-sensitive IRQ
 
 timer2_inst: entity work.timer(rtl)
-	generic map(
-		IRQ_LEVEL_TRIGGERED=>true,
-		IRQ_INVERT=>true
-	)
 	port map(
 		clk_i=>clk_i,
 		rst_i=>rst_i,

verify/lxp32/src/platform/timer.vhd

@@ -16,10 +16,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 entity timer is
-	generic(
-		IRQ_LEVEL_TRIGGERED: boolean:=false;
-		IRQ_INVERT: boolean:=false
-	);
 	port(
 		clk_i: in std_logic;
 		rst_i: in std_logic;
@@ -39,6 +35,9 @@ end entity;
 
 architecture rtl of timer is
 
+signal irq_level_triggered: std_logic:='0';
+signal irq_invert: std_logic:='0';
+
 signal pulses: unsigned(31 downto 0):=(others=>'0');
 signal interval: unsigned(31 downto 0):=(others=>'0');
 signal cnt: unsigned(31 downto 0):=(others=>'0');
@@ -55,7 +54,7 @@ begin
 			cnt<=(others=>'0');
 			elapsed<='0';
 		else
-			if not IRQ_LEVEL_TRIGGERED then
+			if irq_level_triggered='0' then
 				elapsed<='0';
 			end if;
 			if pulses/=X"00000000" or cnt/=X"00000000" then
@@ -87,7 +86,11 @@ begin
 								unsigned(wbs_dat_i(i*8+7 downto i*8));
 							cnt<=(others=>'0');
 						end if;
-						if wbs_adr_i="00"&X"000002" and wbs_dat_i(0)='1' and i=0 then
+						if wbs_adr_i="00"&X"000002" and i=0 then
+							irq_level_triggered<=wbs_dat_i(0);
+							irq_invert<=wbs_dat_i(1);
+						end if;
+						if wbs_adr_i="00"&X"000003" and wbs_dat_i(0)='1' and i=0 then
 							elapsed<='0';
 						end if;
 					end if;
@@ -102,6 +105,6 @@ wbs_dat_o<=std_logic_vector(pulses) when wbs_adr_i="00"&X"000000" else
 	std_logic_vector(interval) when wbs_adr_i="00"&X"000001" else
 	(others=>'-');
 
-elapsed_o<=elapsed when not IRQ_INVERT else not elapsed;
+elapsed_o<=elapsed xor irq_invert;
 
 end architecture;