info.yaml

# Tiny Tapeout project information
project:
  title:        "Serial PDP8"      # Project title
  author:       "Mark G. Arnold"      # Your name
  discord:      "scelbalman_55653"      # Your discord username, for communication and automatically assigning you a Tapeout role (optional)
  description:  "Bit-serial PDP8 adapted from Verilog Digital Computer Design; one-hot states generated by vito"      # One line description of what your project does
  language:     "Verilog" # other examples include SystemVerilog, Amaranth, VHDL, etc
  clock_hz:     50       # Clock frequency in Hz (or 0 if not applicable)

  # How many tiles your design occupies? A single tile is about 167x108 uM.
  tiles: "1x1"          # Valid values: 1x1, 1x2, 2x2, 3x2, 4x2, 6x2 or 8x2

  # Your top module name must start with "tt_um_". Make it unique by including your github username:
  top_module:  "tt_um_markgarnold_pdp8"

  # List your project's source files here.
  # Source files must be in ./src and you must list each source file separately, one per line.
  # Don't forget to also update `PROJECT_SOURCES` in test/Makefile.
  source_files:
    - "project_mga.v"

# The pinout of your project. Leave unused pins blank. DO NOT delete or add any pins.
# This section is for the datasheet/website. Use descriptive names (e.g., RX, TX, MOSI, SCL, SEG_A, etc.).
pinout:
  # Inputs
  ui[0]: "membus"
  ui[1]: "contin"
  ui[2]: ""
  ui[3]: ""
  ui[4]: ""
  ui[5]: ""
  ui[6]: ""
  ui[7]: ""

  # Outputs
  uo[0]: "ma[0]"
  uo[1]: "ma[1]"
  uo[2]: "ma[2]"
  uo[3]: "ma[3]"
  uo[4]: "ma[4]"
  uo[5]: "ma[5]"
  uo[6]: "ma[6]"
  uo[7]: "halt"

  # Bidirectional pins
  uio[0]: "ba[0]"
  uio[1]: "ba[1]"
  uio[2]: "ba[2]"
  uio[3]: "ba[3]"
  uio[4]: "mb"
  uio[5]: "write"
  uio[6]: "unused"
  uio[7]: "unused"

# Do not change!
yaml_version: 6