Memfault Firmware SDK 0.38.0 (Build 1368)

Author: Memfault Inc

CHANGES.md

@@ -1,3 +1,9 @@
+### Changes between Memfault SDK 0.38.0 and SDK 0.37.2 - Feb 1, 2023
+
+#### :rocket: New Features
+
+- Enable coredumps on the ESP32-S2 and ESP32-S3 chips.
+
 ### Changes between Memfault SDK 0.37.2 and SDK 0.37.1 - Jan 31, 2023
 
 #### :chart_with_upwards_trend: Improvements

VERSION

@@ -1,2 +1,2 @@
-BUILD ID: 1352
-GIT COMMIT: a083eca61
+BUILD ID: 1368
+GIT COMMIT: 4a9233626

components/include/memfault/version.h

@@ -19,7 +19,7 @@ typedef struct {
   uint8_t patch;
 } sMfltSdkVersion;
 
-#define MEMFAULT_SDK_VERSION   { .major = 0, .minor = 37, .patch = 2 }
+#define MEMFAULT_SDK_VERSION   { .major = 0, .minor = 38, .patch = 0 }
 
 #ifdef __cplusplus
 }

components/panics/src/memfault_coredump.c

@@ -67,17 +67,29 @@ typedef MEMFAULT_PACKED_STRUCT MfltTraceReasonBlock {
 
 #define MEMFAULT_MACHINE_TYPE_SUBTYPE_OFFSET 16
 
+//! ESP32
 #define MEMFAULT_MACHINE_TYPE_XTENSA 94
 
+//! ESP8266
 #define MEMFAULT_MACHINE_TYPE_XTENSA_LX106 \
   ((1 << MEMFAULT_MACHINE_TYPE_SUBTYPE_OFFSET) | MEMFAULT_MACHINE_TYPE_XTENSA)
 
-typedef enum MfltCoredumpMachineType  {
+//! ESP32-S2
+#define MEMFAULT_MACHINE_TYPE_XTENSA_LX7 \
+  ((2 << MEMFAULT_MACHINE_TYPE_SUBTYPE_OFFSET) | MEMFAULT_MACHINE_TYPE_XTENSA)
+
+//! ESP32-S3
+#define MEMFAULT_MACHINE_TYPE_XTENSA_LX7_DUAL \
+  ((3 << MEMFAULT_MACHINE_TYPE_SUBTYPE_OFFSET) | MEMFAULT_MACHINE_TYPE_XTENSA)
+
+typedef enum MfltCoredumpMachineType {
   kMfltCoredumpMachineType_None = 0,
   kMfltCoredumpMachineType_ARM = 40,
   kMfltCoredumpMachineType_Aarch64 = 183,
   kMfltCoredumpMachineType_Xtensa = MEMFAULT_MACHINE_TYPE_XTENSA,
-  kMfltCoredumpMachineType_XtensaLx106 = MEMFAULT_MACHINE_TYPE_XTENSA_LX106
+  kMfltCoredumpMachineType_XtensaLx106 = MEMFAULT_MACHINE_TYPE_XTENSA_LX106,
+  kMfltCoredumpMachineType_XtensaLx7 = MEMFAULT_MACHINE_TYPE_XTENSA_LX7,
+  kMfltCoredumpMachineType_XtensaLx7Dual = MEMFAULT_MACHINE_TYPE_XTENSA_LX7_DUAL,
 } eMfltCoredumpMachineType;
 
 typedef MEMFAULT_PACKED_STRUCT MfltMachineTypeBlock {
@@ -220,23 +232,30 @@ static eMfltCoredumpBlockType prv_region_type_to_storage_type(eMfltCoredumpRegio
 }
 
 static eMfltCoredumpMachineType prv_get_machine_type(void) {
+  return
 #if defined(MEMFAULT_UNITTEST)
-  return kMfltCoredumpMachineType_None;
+    kMfltCoredumpMachineType_None
+#elif MEMFAULT_COMPILER_ARM
+    kMfltCoredumpMachineType_ARM
+#elif defined(__aarch64__)
+    kMfltCoredumpMachineType_Aarch64
+#elif defined(__XTENSA__) && defined(__XTENSA_WINDOWED_ABI__) && defined(__XTENSA_SOFT_FLOAT__)
+    // ESP32-S2 has this unique compiler-defined symbol
+    kMfltCoredumpMachineType_XtensaLx7
+#elif defined(__XTENSA__) && defined(__XTENSA_WINDOWED_ABI__) && defined(CONFIG_IDF_TARGET_ESP32S3)
+    // rely on Kconfig provided flag for ESP32-S3; compiler defined symbols are identical to ESP32.
+    // ❯ diff -duw <(xtensa-esp32-elf-gcc -dM -E - < /dev/null)  <(xtensa-esp32s3-elf-gcc -dM -E - < /dev/null)
+    kMfltCoredumpMachineType_XtensaLx7Dual
+#elif defined(__XTENSA__) && defined(__XTENSA_WINDOWED_ABI__)
+    // default xtensa windowed target is vanilla ESP32
+    kMfltCoredumpMachineType_Xtensa
+#elif defined(__XTENSA__)
+    // finally, ESP8266
+    kMfltCoredumpMachineType_XtensaLx106
 #else
-#  if MEMFAULT_COMPILER_ARM
-  return kMfltCoredumpMachineType_ARM;
-#  elif defined(__aarch64__)
-  return kMfltCoredumpMachineType_Aarch64;
-#  elif defined(__XTENSA__)
-  # if defined(__XTENSA_WINDOWED_ABI__)
-    return kMfltCoredumpMachineType_Xtensa;
-  # else
-    return kMfltCoredumpMachineType_XtensaLx106;
-  # endif
-# else
-#    error "Coredumps are not supported for target architecture"
-#  endif
+  #error "Coredumps are not supported for target architecture"
 #endif
+    ;
 }
 
 static bool prv_write_device_info_blocks(sMfltCoredumpWriteCtx *ctx) {

ports/esp_idf/memfault/common/memfault_fault_handler.c

@@ -74,14 +74,12 @@ void __wrap_esp_core_dump_to_flash(XtExcFrame *fp) {
       fp->a15,
     },
     .sar = fp->sar,
-#if CONFIG_IDF_TARGET_ESP32
+    // the below registers are not available on the esp32s2; leave them zeroed
+    // in the coredump
+#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S3
     .lbeg = fp->lbeg,
     .lend = fp->lend,
     .lcount = fp->lcount,
-#elif CONFIG_IDF_TARGET_ESP32S2
-    // TODO implement fault capture for the ESP32-S2
-#elif CONFIG_IDF_TARGET_ESP32S3
-    // TODO implement fault capture for the ESP32-S3
 #endif
     .exccause = fp->exccause,
     .excvaddr = fp->excvaddr,

ports/esp_idf/memfault/common/memfault_platform_coredump.c

@@ -85,9 +85,22 @@ const sMfltCoredumpRegion *memfault_platform_coredump_get_regions(
     const sCoredumpCrashInfo *crash_info, size_t *num_regions) {
   static sMfltCoredumpRegion s_coredump_regions[1];
 
+  // The ESP32S2 + S3 have a different memory map than the ESP32; IRAM and DRAM
+  // share the same pysical SRAM, but are mapped at different addresses. We need
+  // to account for the placement of IRAM data, which offsets the start of
+  // placed DRAM.
+  //
+  // https://www.espressif.com/sites/default/files/documentation/esp32-s2_technical_reference_manual_en.pdf#subsubsection.3.3.2
+  // https://www.espressif.com/sites/default/files/documentation/esp32-s3_technical_reference_manual_en.pdf#subsubsection.4.3.2
+#if defined(CONFIG_IDF_TARGET_ESP32S3) || defined(CONFIG_IDF_TARGET_ESP32S2)
+  // use this symbol defined by the linker to find the start of DRAM
+  extern uint32_t _data_start;
+  const uint32_t esp32_dram_start_addr = (uint32_t)&_data_start;
+#else
   const uint32_t esp32_dram_start_addr = SOC_DMA_LOW;
+#endif
 
-  size_t dram_collection_len = SOC_DMA_HIGH - SOC_DMA_LOW;
+  size_t dram_collection_len = SOC_DMA_HIGH - esp32_dram_start_addr;
   const esp_partition_t *core_part = prv_get_core_partition();
   if (core_part != NULL) {
     // NB: Leave some space in storage for other regions collected by the SDK