Merge branch 'tc-l2' into dev

Author: maksyuki

README.md

@@ -1,7 +1,7 @@
 <p align="center">
     <img width="200px" src="./.images/tree_core_logo.svg" align="center" alt="Tree Core CPU" />
     <h1 align="center">TreeCore CPU</h1>
-    <p align="center">A series of RISCV soft core processor written from scratch</p>
+    <p align="center">A series of RISCV soft core processors written from scratch</p>
 </p>
 <p align="center">
     <a href="./LICENSE">
@@ -19,15 +19,23 @@
 </p>
 
 ## Overview
-the TreeCore L2 is the riscv64 software core developed under the [Open Source Chip Project by University (OSCPU)](https://github.com/OSCPU). OSCPU was initiated by ICTCAS(**_Institute of computing Technology, Chinese Academy of Sciences_**), which aims to make students use all open-source toolchain to design, develop open-source chips by themselves. It also can be called "One Life, One Chip" project in Chinese which has achieved two season. Now Season 3 is in progress in 2021.
+The TreeCore processors are the riscv64 software core developed under the [Open Source Chip Project by University (OSCPU)](https://github.com/OSCPU). OSCPU was initiated by ICTCAS(**_Institute of computing Technology, Chinese Academy of Sciences_**), which aims to make students use all open-source toolchain to design, develop open-source chips by themselves. It also can be called "One Life, One Chip" project in Chinese which has achieved two season. Now Season 3 is in progress in 2021.
+
+Now the TreeCore has two version, TreeCoreL1(**_TreeCore Learning Core 1_**) and TreeCoreL2(**_TreeCore Learning Core 2_**).
 
 ## Feature
-* 64-bits single-issue, five-stage pipeline RISCV ISA CPU core.
-* support RISCV integer(I) instruction set.
-* supports machine mode privilege levels.
-* supports AXI4 inst and mem acess.
-* can boot rt-thread.
-* develop under all open-source toolchain.
+TreeCoreL1
+* 64-bits single period riscv core
+* written by verilog
+
+TreeCoreL2
+* 64-bits single-issue, five-stage pipeline riscv core
+* written by chisel3
+* support RISCV integer(I) instruction set
+* supports machine mode privilege levels
+* supports AXI4 inst and mem acess
+* can boot rt-thread
+* develop under all open-source toolchain
 
 ## Develop Schedule
 Now, the develop schedule is recorded by the **Tencent Document**. You can click this link [schedule table](https://docs.qq.com/sheet/DY3lORW5Pa3pLRFpT?newPad=1&newPadType=clone&tab=BB08J2) to view it.
@@ -56,17 +64,17 @@ Now, the develop schedule is recorded by the **Tencent Document**. You can click
 #### Enviroment setup(ubuntu 20.04 LTS)
 install verilator, mill and dep lib: 
 ```bash
-$ sudo apt-get install g++-riscv64-linux-gnu binutils-riscv64-linux-gnu
-$ ./setup.sh -a
+sudo apt-get install g++-riscv64-linux-gnu binutils-riscv64-linux-gnu
+./setup.sh -a
 ```
 
 change the sim memory from 8G to 256MB. need to enter 'make menuconfig' and modify [Memory - Configuration]->[Memory size] to '0x10000000' manually.
 cd in root rtl dir
 ```bash
-$ make nemuBuild
-$ make diffBuild
-$ make difftestBuild
-$ make demoTest
+make nemuBuild
+make diffBuild
+make difftestBuild
+make demoTest
 ```
 
 ### Software test

README_zh-CN.md

@@ -1,7 +1,7 @@
 <p align="center">
     <img width="200px" src="./.images/tree_core_logo.svg" align="center" alt="木心处理器" />
     <h1 align="center">木心处理器</h1>
-    <p align="center">一款从零开始编写的RISC-V软核处理器。</p>
+    <p align="center">一系列从零开始编写的RISC-V软核处理器</p>
 </p>
 <p align="center">
     <a href="./LICENSE">
@@ -21,10 +21,6 @@
 
 ## 前言
 
-我是在大三下学期的时候（即2016年的夏天）第一次听到了RISC-V这个词，那会儿我舍友刚好参加了学院组织的《计算机体系结构》试点班，**而他们的任务就是要基于RISC-V指令集去设计一款简单的软核CPU**，当时我只知道它是由伯克利大学推出的开源RISC指令集，觉得跟我们普通班学习所要用到的MIPS指令集类似，所以就没有太放在心上。可是令人没有想到的是，经过短短几年的发展，RISC-V指令集已经得到了全世界众多互联网和半导体巨头的支持，而且有越来越多的研究机构和初创公司开始基于它来设计自己的专有处理器，我认为目前的RISC-V就像早期的Linux内核，虽然功能和性能还非常有限，但是借助开源协作的力量，**我相信总有一天RISC-V也能在某些领域迎来一场足以改变旧有格局的革命**。因此为了不被即将到来的新时代所抛弃，作为一名业余硬件爱好者，我觉得自己还是很有必要好好学习一下RISC-V指令集的，没准以后有机会还能为国产自主可控处理器的设计和研发贡献自己的一份力量！
-
-古人曾经说过：**纸上得来终觉浅，绝知此事要躬行**，既然自己决定要学习RISC-V，那就必须亲身实践才能搞明白，而对于这种处于计算机体系结构底层的项目来说，没有什么能够比自己从零实现一遍更好的方法了，于是抱着这种想法我开始在网上搜集资料，结果比较令人失望，虽说国外与RISC-V相关的开源项目有不少，但是其中很多都是用Chisel这种高级硬件构建语言来实现的，学习门槛非常高，再加上为了追求整体的性能，一些CPU的系统架构设计得非常复杂（如采用五级以上流水线、多核处理、乱序执行等），初学者想入门非常困难。所以经过深思熟虑后，我决定从零编写一款系统**架构足够精简、代码足够清晰、封装足够优秀**的开源处理器项目，希望它能像从众多微控制器中脱颖而出的Arduino一样，让更多的硬件爱好者可以快速上手体验，并基于此开发很多有意思的应用，未来在软硬件生态环境的互相促进下，也许会有更多的人喜欢上CPU开发并愿意花时间去钻研，如果真的能够做到如此，我也就心满意足了。
-
 ## 概述
 
 ## 使用